Datasheet > GS71116AGP-10

GS71116AGP-10

更新时间： 2024-11-05 23:16:35

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
16页	385K
描述
1Mb Asynchronous SRAM

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中文翻译

获取价格

数据手册

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GS71116AGP-10 数据手册

GS71116ATP/J/U

7, 8, 10, 12 ns

SOJ, TSOP, FP-BGA

Commercial Temp

Industrial Temp

64K x 16

1Mb Asynchronous SRAM

3.3 V V

Center V and V

Features

• Fast access time: 7, 8, 10, 12 ns

• CMOS low power operation: 145/125/100/85 mA at

minimum cycle time

SOJ 64K x 16-Pin Configuration

• Single 3.3 V power supply

• All inputs and outputs are TTL-compatible

• Byte control

• Fully static operation

• Industrial Temperature Option: –40° to 85°C

• Package line up

Top view

DQ1

DQ2

DQ3

DQ4

V_DD

DQ16

DQ15

DQ14

400 mil, 44-pin SOJ package

TP: 400 mil, 44-pin TSOP Type II package

GP: Pb-Free 400 mil, 3244-pin TSOP Type II package

U: 6 mm x 8 mm Fine Pitch Ball Grid Array package

GU: Pb-Free 6 mm x 8 mm Fine Pitch Ball Grid Array

package

DQ13

V_SS

V_DD

DQ12

DQ11

DQ10

DQ9

44-pin

SOJ

V_SS

DQ5

DQ6

DQ7

DQ8

• Pb-Free TSOP-II and FP-BGA packages available

Description

The GS71116A is a high speed CMOS static RAM organized

as 65,536-words by 16-bits. Static design eliminates the need

for external clocks or timing strobes. Operating on a single

3.3 V power supply and all inputs and outputs are TTL-

compatible. The GS71116A is available in a 6 mm x 8 mm

Fine Pitch BGA package, as well as in 400 mil SOJ and 400

mil TSOP Type-II packages.

A15

A14

A13

A12

A10

A11

Package J

Pin Descriptions

Symbol

A0–A15

DQ1–DQ16

Description

Address input

Data input/output

Chip enable input

Lower byte enable input

(DQ1 to DQ8)

Upper byte enable input

(DQ9 to DQ16)

Write enable input

Output enable input

+3.3 V power supply

Ground

No connect

Rev: 1.07 12/2004

1/16

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...16

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