Datasheet > GS4576C09L-25I

GS4576C09L-25I

更新时间： 2024-11-07 00:43:31

品牌	Logo	应用领域
GSI		动态存储器
页数	文件大小	规格书
63页	2120K
描述
576Mb CIO Low Latency DRAM (LLDRAM II)

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中文翻译

获取价格

数据手册

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GS4576C09L-25I 数据手册

GS4576C09/18/36L

533 MHz–300 MHz

144-Ball BGA

Commercial Temp

Industrial Temp

64M x 9, 32M x 18, 16M x 36

576Mb CIO Low Latency DRAM (LLDRAM II)

2.5 V V_EXT

1.8 V V_DD

1.5 V or 1.8 V V_DDQ

Features

Introduction

• Pin- and function-compatible with Micron RLDRAM® II

• 533 MHz DDR operation (1.067Gb/s/pin data rate)

• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency)

• 16M x 36, 32M x 18, and 64M x 9 organizations available

• 8 banks

• Reduced cycle time (15 ns at 533 MHz)

• Address Multiplexing (Nonmultiplexed address option

available)

• SRAM-type interface

• Programmable Read Latency (RL), row cycle time, and burst

sequence length

• Balanced Read and Write Latencies in order to optimize data

bus utilization

The GSI Technology 576Mb Low Latency DRAM 

(LLDRAM II) is a high speed memory device designed for

high address rate data processing typically found in networking

and telecommunications applications. The 8-bank architecture

and low tRC allows access rates formerly only found in

SRAMs.

The Double Data Rate (DDR) I/O interface provides high

bandwidth data transfers, clocking out two beats of data per

clock cycle at the I/O balls. Source-synchronous clocking can

be implemented on the host device with the provided free-

running data output clock.

• Data mask for Write commands

Commands, addresses, and control signals are single data rate

signals clocked in by the True differential input clock

transition, while input data is clocked in on both crossings of

the input data clock(s).

• Differential input clocks (CK, CK)

• Differential input data clocks (DKx, DKx)

• On-chip DLL generates CK edge-aligned data and output

data clock signals

• Data valid signal (QVLD)

Read and Write data transfers always in short bursts. The burst

length is programmable to 2, 4 or 8 by setting the Mode

• 32 ms refresh (16K refresh for each bank; 128K refresh

command must be issued in total each 32 ms)

• 144-ball BGA package

• HSTL I/O (1.5 V or 1.8 V nominal)

The device is supplied with 2.5 V V

and 1.8 V V for the

EXT DD

• 25–60 matched impedance outputs

core, and 1.5 V or 1.8 V for the HSTL output drivers.

• 2.5 V V , 1.8 V V , 1.5 V or 1.8 V V I/O

DDQ

EXT

• On-die termination (ODT) R

Internally generated row addresses facilitate bank-scheduled

refresh.

• Commerical and Industrial Temperature

Commercial (+0° T +95°C)

The device is delivered in an efficent BGA 144-ball package.

Industrial (–40° T +95°C)

Rev: 1.04 11/2013

1/62

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...63

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与GS4576C09L-25I相关器件

型号	品牌	获取价格	描述	数据表
GS4576C09L-33	GSI	获取价格	DDR DRAM, 64MX9, CMOS, PBGA144, UBGA-144
GS4576C09L-33IT	GSI	获取价格	DDR DRAM, 64MX9, CMOS, PBGA144, UBGA-144
GS4576C18GL-18	GSI	获取价格	DDR DRAM, 32MX18, CMOS, PBGA144, ROHS COMPLIANT, UBGA-144
GS4576C18GL-18I	GSI	获取价格	DDR DRAM, 32MX18, CMOS, PBGA144, ROHS COMPLIANT, UBGA-144
GS4576C18GL-18IT	GSI	获取价格	DDR DRAM, 32MX18, CMOS, PBGA144, ROHS COMPLIANT, UBGA-144
GS4576C18GL-18T	GSI	获取价格	DDR DRAM, 32MX18, CMOS, PBGA144, ROHS COMPLIANT, UBGA-144
GS4576C18GL-24	GSI	获取价格	576Mb CIO Low Latency DRAM (LLDRAM II)
GS4576C18GL-24IT	GSI	获取价格	DDR DRAM, 32MX18, CMOS, PBGA144, ROHS COMPLIANT, UBGA-144
GS4576C18GL-25	GSI	获取价格	576Mb CIO Low Latency DRAM (LLDRAM II)
GS4576C18GL-33	GSI	获取价格	DDR DRAM, 32MX18, CMOS, PBGA144, ROHS COMPLIANT, UBGA-144

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