Datasheet > GDP2BFLM-CB

GDP2BFLM-CB

更新时间： 2023-12-06 20:07:47

品牌	Logo	应用领域
兆易创新 - GIGADEVICE		通信动态存储器双倍数据速率监控电视
页数	文件大小	规格书
96页	2965K
描述
在网络通信、电视、监控、机顶盒、工业、智慧家庭等领域，利基型DDR3L是应用极为广泛的DRAM系统解决方案之一。兆易创新利基型DDR3L兼容1.5V/1.35V电压供电，读写速率为1866Mbps

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GDP2BFLM-CB 数据手册

DDR3L SDRAM

1 FEATURES

GDP2BFLM GDP2A8LM

◆ Power supply: V_DD= V_DDQ= 1.35V (1.283V - 1.45V)

◆ Backward compatible to V_DD= V_DDQ= 1.5V ± 0.075V

- Supports DDR3L devices to be backward compatible in 1.5V application

◆ Package: 96-Ball FBGA (x16) 78-Ball FBGA(x8)

◆ Array configuration: 8 Banks

◆ 8n-Bit prefetch architecture

◆ Differential clock inputs (CK, CK#)

◆ Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals

◆ Programmable CAS (READ) latency (CL)

◆ Programmable posted CAS additive latency (AL)

◆ Programmable CAS (WRITE) latency (CWL)

◆ Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])

◆ Selectable BC4 or BL8 on-the-fly (OTF)

◆ Self refresh mode

◆ Operating case temperature: -40℃ ≤ T_CASE≤ 95℃

◆ Average refresh period:

-7.8us at 0℃ ≤ T_CASE≤ 85℃

-3.9us at 85℃＜T_CASE≤ 95℃

◆ JEDEC JESD79-3F compliant

◆ RoHS compliant

Note:

1. The functionality described and the timing specifications included in this data sheet are for the DLL enabled mode of

operation.

DS-00823-GDP2BFLM-Rev1.1

2023/6/28

1 2 3 456 7 8...96

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