DDR3L SDRAM
GDP2BFLM GDP2A8LM
Contents
1 FEATURES.............................................................................................................................5
1.1 Address Table.......................................................................................................................................... 6
2 ORDERING INFORMATION ..................................................................................................7
2.1 Part Number Decoding............................................................................................................................ 7
2.2 Valid Part Numbers.................................................................................................................................. 8
3 PACKAGE INFORMATION....................................................................................................9
3.1 Package 78-Ball FBGA (x8) .................................................................................................................... 9
3.2 Package 96-Ball FBGA (x16) ................................................................................................................ 10
4 BALL ASSIGNMENTS......................................................................................................... 11
4.1 78-Ball FBGA (x8) ball Assignments..................................................................................................... 11
4.2 96-Ball FBGA (x16) Ball Assignments................................................................................................... 12
4.3 Ball Description...................................................................................................................................... 13
5 FUNCTIONAL BLOCK DIAGRAMS ....................................................................................15
6 ABSOLUTE MAXIMUM RATINGS.......................................................................................16
6.1 Absolute Maximum DC Ratings............................................................................................................. 16
6.2 Recommended DC Operating Conditions............................................................................................. 16
6.3 DRAM Component Operating Temperature Range.............................................................................. 17
7 AC AND DC INPUT MEASUREMENT LEVELS..................................................................18
7.1 AC and DC Logic Input Levels for Single-ended Signals...................................................................... 18
7.1.1 AC and DC Input Levels for Single-ended Command and Address Signals ..........................................18
7.1.2 AC and DC Input Levels for Single-ended Data Signals.........................................................................19
7.2 VREF Tolerances..................................................................................................................................... 21
7.3 AC and DC Logic Input Levels for Differential Signals.......................................................................... 22
DS-00823-GDP2BFLM-Rev1.1
2
2023/6/28
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