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GAL16V8B-25LP PDF预览

GAL16V8B-25LP

更新时间: 2024-01-24 01:31:21
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件光电二极管输入元件时钟
页数 文件大小 规格书
23页 395K
描述
High Performance E2CMOS PLD Generic Array Logic

GAL16V8B-25LP 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:PLASTIC, DIP-20
针数:20Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.18Is Samacsys:N
其他特性:REGISTER PRELOAD; POWER-UP RESET架构:PAL-TYPE
最大时钟频率:37 MHzJESD-30 代码:R-PDIP-T20
JESD-609代码:e0长度:26.125 mm
专用输入次数:8I/O 线路数量:8
输入次数:18输出次数:8
产品条款数:64端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
组织:8 DEDICATED INPUTS, 8 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
可编程逻辑类型:EE PLD传播延迟:25 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Programmable Logic Devices最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

GAL16V8B-25LP 数据手册

 浏览型号GAL16V8B-25LP的Datasheet PDF文件第14页浏览型号GAL16V8B-25LP的Datasheet PDF文件第15页浏览型号GAL16V8B-25LP的Datasheet PDF文件第16页浏览型号GAL16V8B-25LP的Datasheet PDF文件第18页浏览型号GAL16V8B-25LP的Datasheet PDF文件第19页浏览型号GAL16V8B-25LP的Datasheet PDF文件第20页 
Specifications GAL16V8  
POWER-UP RESET  
Vcc (min.)  
Vcc  
t
su  
t
wl  
CLK  
t
pr  
Internal Register  
Reset to Logic "0"  
INTERNAL REGISTER  
Q - OUTPUT  
FEEDBACK/EXTERNAL  
OUTPUT REGISTER  
Device Pin  
Reset to Logic "1"  
Circuitry within the GAL16V8 provides a reset signal to all reg-  
isters during power-up. All internal registers will have their Q  
outputs set low after a specified time (tpr, 1µs MAX). As a result,  
the state on the registered output pins (if they are enabled) will  
always be high on power-up, regardless of the programmed  
polarity of the output pins. This feature can greatly simplify state  
machine design by providing a known state on power-up. Be-  
cause of the asynchronous nature of system power-up, some  
conditions must be met to guarantee a valid power-up reset of the  
device. First, the VCC rise must be monotonic. Second, the clock  
input must be at static TTL level as shown in the diagram during  
power up. The registers will reset within a maximum of tpr time.  
As in normal system operation, avoid clocking the device until all  
input and feedback path setup times have been met. The clock  
must also meet the minimum pulse width requirements.  
INPUT/OUTPUT EQUIVALENT SCHEMATICS  
PIN  
PIN  
Feedback  
Vcc  
Active Pull-up  
Circuit  
Active Pull-up  
Circuit  
Vcc  
Tri-State  
Control  
Vref  
Vcc  
Vcc  
Vref  
ESD  
Protection  
Circuit  
Data  
Output  
PIN  
PIN  
ESD  
Protection  
Circuit  
Feedback  
(To Input Buffer)  
Typ. Vref = 3.2V  
Typ. Vref = 3.2V  
Typical Input  
Typical Output  
1996 Data Book  
3-81  

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