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FX629 PDF预览

FX629

更新时间: 2024-10-27 22:48:55
品牌 Logo 应用领域
CMLMICRO 解码器编解码器
页数 文件大小 规格书
10页 95K
描述
Delta Modulation Codec

FX629 数据手册

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Pin Number Function  
FX629J  
No connection  
12  
Decoder Output : The recovered analogue signal is output at this pin, it is the buffered  
output of a bandpass filter and requires external components. During "Powersave" this  
output is o/c.  
13  
No connection  
14  
15  
Powersave : A logical '0' at this pin puts most parts of the codec into a quiescent non-  
operational state. When at a logical '1' the codec operates normally. Internal 1MPullup.  
Decoder Force Idle : A logical '0' at this pin gates a 0101...pattern internally to the  
decoder so that the decoder output goes to VDD/2. When this pin is at a logical '1' the  
decoder operates as normal. Internal 1MPullup.  
16  
Decoder Input : The received digital signal input. Internal 1MPullup.  
17  
18  
Decoder Data Clock : A Logic I/O port. External decode clock input or internal data clock  
output, dependant upon clock mode 1, 2 inputs, see Clock Mode pins.  
Algorithm : A logical '1' at this pin sets this device for a 3-bit companding algorithm. A  
logical '0' sets a 4-bit companding algorithm. Internal 1MPullup.  
19  
Clock Mode 2 :  
20  
21  
Clock Mode 1  
Clock Mode 2  
Facility  
External clocks  
Internal, 64kb/s = f ÷ 16  
Internal, 32kb/s = f ÷ 32  
Internal, 16kb/s = f ÷ 64  
Clock Mode 1 :  
Internal 1MΩ  
Pullups.  
0
0
1
1
0
1
0
1
Clock rates refer to f = 1.024 MHz Xtal/clock input. During internal operation the data clock  
frequencies are available at the ports for external circuit synchronization.  
Independent or common data rate inputs to Encode and Decode data clock ports may be  
employed in the External Clocks mode. Optimum performance will be achieved when the  
applied external clocks are synchronous with the master Xtal/clock, and a sub-multiple of  
128kHz.  
VDD : Positive Supply. A single + 5 volt power supply is required.  
22  
3

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