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FT28HC256PM-15 PDF预览

FT28HC256PM-15

更新时间: 2022-10-12 13:40:48
品牌 Logo 应用领域
福思力 - FORCE 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
23页 2123K
描述
5 Volt, Byte Alterable EEPROM

FT28HC256PM-15 数据手册

 浏览型号FT28HC256PM-15的Datasheet PDF文件第4页浏览型号FT28HC256PM-15的Datasheet PDF文件第5页浏览型号FT28HC256PM-15的Datasheet PDF文件第6页浏览型号FT28HC256PM-15的Datasheet PDF文件第8页浏览型号FT28HC256PM-15的Datasheet PDF文件第9页浏览型号FT28HC256PM-15的Datasheet PDF文件第10页 
FT28HC256  
RESETTING SOFTWARE DATA PROTECTION  
Figure 8. Reset Software Data Protection Timing Sequence  
V
CC  
AAA  
5555  
55  
2AAA  
80  
5555  
AA  
5555  
55  
2AAA  
20  
5555  
Standard  
Operating  
Mode  
Data  
Address  
t
WC  
CE  
WE  
Figure 9. Write Sequence for resetting Software  
Data Protection  
In the event the user wants to deactivate the software  
data protection feature for testing or reprogramming in  
an EEPROM programmer, the following six step algo-  
rithm will reset the internal protection circuit. After t  
the FT28HC256 will be in standard operating mode.  
,
WC  
Write Data AA  
to Address  
5555  
Note: Once initiated, the sequence of write operations  
should not be interrupted.  
Write Data 55  
to Address  
2AAA  
SYSTEM CONSIDERATIONS  
Because the FT28HC256 is frequently used in large  
memory arrays, it is provided with a two line control  
architecture for both read and write operations. Proper  
usage can provide the lowest possible power dissipa-  
tion, and eliminate the possibility of contention where  
multiple I/O pins share the same bus.  
Write Data 80  
to Address  
5555  
Write Data AA  
to Address  
5555  
To gain the most benefit, it is recommended that CE be  
decoded from the address bus and be used as the pri-  
mary device selection input. Both OE and WE would  
then be common among all devices in the array. For a  
read operation, this assures that all deselected devices  
are in their standby mode, and that only the selected  
device(s) is/are outputting data on the bus.  
Write Data 55  
to Address  
2AAA  
Because the FT28HC256 has two power modes ,  
standby and active, proper decoupling of the memory  
array is of prime concern. Enabling CE will cause tran-  
sient current spikes. The magnitude of these spikes is  
dependent on the output capacitive loading of the l/Os.  
Therefore, the larger the array sharing a common bus,  
the larger the transient spikes. The voltage peaks  
associated with the current transients can be sup-  
pressed by the proper selection and placement of  
decoupling capacitors. As a minimum, it is recommended  
Write Data 20  
to Address  
5555  
After t  
,
WC  
Re-Enters  
Unprotected  
State  
Characteristics subject to change without notice. 7 of 23  
REV 1.0  

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