FT28HC256
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
Last
Write
WE
CE
OE
V
HIGH Z
OH
I/O
6
*
*
V
OL
Ready
* I/O Beginning and ending state of I/O will vary.
6
6
Figure 5. Toggle Bit Software Flow
HARDWARE DATA PROTECTION
¬
The FT28HC256 provides two hardware features that
protect nonvolatile data from inadvertent writes.
Last Write
Yes
– Default V Sense—All write functions are inhibited
CC
when V is 3.5V typically.
CC
– Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
Load Accum
From Addr n
SOFTWARE DATA PROTECTION
The FT28HC256 offers a softw are-controlled data pro-
tection feature. The FT28HC256 is shipped from FT
with the software data protection NOT ENABLED; that
is, the device will be in the standard operating mode. In
this mode data should be protected during power-up/
down operations through the use of e xternal circuits.
The host would then have open read and write access
Compare
Accum with
Addr n
No
Compare
ok?
of the device once V
was stable.
CC
Yes
The FT28HC256 can be automatically protected during
power-up and power-down (without the need for exter-
nal circuits) by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first w ite operation, utilising the soft-
ware algor ithm. This circuit is non volatile, and will
remain set for the life of the device unless the reset
command is issued.
FT28C256
Ready
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an array
comprised of multiple FT28HC256 memories that is
frequently updated. The timing diagram in Figure 4
illustrates the sequence of events on the bus. The soft-
ware flow diagram in Figure 5 illustrates a method for
polling the Toggle Bit.
Once the software protection is enabled, the FT28HC256 is
also protected from inadvertent and accidental writes in the
powered-up state. That is, the software algorithm must be
issued prior to writing additional data to the device.
Characteristics subject to change without notice. 5 of 23
REV 1.0