Datasheet > FS61857-01

FS61857-01

更新时间： 2024-02-04 20:43:12

品牌	Logo	应用领域
AMI		光电二极管
页数	文件大小	规格书
7页	103K
描述
Clock Driver, CMOS, PDSO48,

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技术参数
数据手册

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FS61857-01 技术参数

生命周期：	Obsolete	包装说明：	TSSOP, TSSOP48,.3,20
Reach Compliance Code：	unknown	风险等级：	5.84
JESD-30 代码：	R-PDSO-G48	端子数量：	48
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP48,.3,20	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	电源：	2.5 V
认证状态：	Not Qualified	子类别：	Clock Drivers
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	DUAL	Base Number Matches：	1

FS61857-01 数据手册

FS61857-01

1:10 HSTL Zero-Delay Clock Buffer IC

AMERICAN MICROSYSTEMS, INC.

Advance Information

November 2000

4.0 Electrical Specifications

Table 3: Absolute Maximum Ratings

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at

these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,

functionality, and reliability.

PARAMETER

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage, dc, Clock Buffers (GND = ground)

Supply Voltage, dc, Core

Input Voltage, dc

AV_DD

V_DD

V_I

V_O

I_IK

I_OK

T_S

T_A

GND-0.5

-50

V_DD+0.5

Output Voltage, dc

Input Clamp Current, dc (V_I< 0 or V_I> V_DD

)

°C

Output Clamp Current, dc (V_I< 0 or V_I> V_DD

)

-50

-65

-55

Storage Temperature Range (non-condensing)

Ambient Temperature Range, Under Bias

Junction Temperature

Lead Temperature (soldering, 10s)

Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)

150

125

260

T_J

CAUTION: ELECTROSTATIC SENSITIVE DEVICE

Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy

electrostatic discharge.

Table 4: Operating Conditions

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

TYP.

MAX.

UNITS

AV_DD

V_DD

T_A

Core

Outputs

2.3

2.5

2.7

Supply Voltage

Ambient Operating Temperature Range

°C

Frequency range over which PLL

acquires lock

Frequency range where all timing

parameter specification are met

170

Input Frequency (CKP / CKN)

f_CLK

MHz

Input Duty Cycle

Input Rise/Fall Time

Spread-Spectrum Modulation Frequency

Spread-Spectrum Modulation Index

Output Load Capacitance

CKP / CKN

CKP / CKN (over 20% to 80%)

0.375

1.5

-0.5

MHz

t_r, t_f

f_m

δ_m

C_L

ISO9001

QS9000

1 234 5 6 7

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