Datasheet > FS61857-01

FS61857-01

更新时间： 2024-01-01 17:42:38

品牌	Logo	应用领域
AMI		光电二极管
页数	文件大小	规格书
7页	103K
描述
Clock Driver, CMOS, PDSO48,

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数据手册

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FS61857-01 技术参数

生命周期：	Obsolete	包装说明：	TSSOP, TSSOP48,.3,20
Reach Compliance Code：	unknown	风险等级：	5.84
JESD-30 代码：	R-PDSO-G48	端子数量：	48
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP48,.3,20	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	电源：	2.5 V
认证状态：	Not Qualified	子类别：	Clock Drivers
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	DUAL	Base Number Matches：	1

FS61857-01 数据手册

FS61857-01

1:10 HSTL Zero-Delay Clock Buffer IC

AMERICAN MICROSYSTEMS, INC.

Advance Information

November 2000

Table 2: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI^U= Input with Internal Pull-Up; DI_D= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,

DO = Digital Output; P = Power/Ground; # = Active Low pin

TYPE

NAME

DESCRIPTION

2.5V PLL power supply / Test mode enable.

AVDD

This pin provides the power supply to the internal PLL. When pulled low, the PLL is by-

passed and the output clocks directly follow the input clock

AGND

CKP / CKN

FBINP / FBINN

FBOUTP / FBOUTN

PWRDWN#

YP0 / YN0

PLL ground

13 / 14

36 / 35

32 / 33

Reference clock input (true / complementary)

Feedback input (true / complementary)

Feedback output (true / complementary)

Asynchronous power-down input shuts down PLL and tristates all outputs

3 / 2

5 / 6

YP1 / YN1

10 / 9

20 / 19

22 / 23

46 / 47

44 / 43

39 / 40

29 / 30

27 / 26

YP2 / YN2

YP3 / YN3

YP4 / YN4

YP5 / YN5

YP6 / YN6

YP7 / YN7

YP8 / YN8

YP9 / YN9

Clock outputs (true / complementary)

1, 7, 8, 18, 24, 25,

31, 41, 42, 48

4, 11, 12, 15, 21,

28, 34, 38, 45

GND

VDD

Ground for all clock outputs

2.5V power supply for all clock outputs

3.1

PLL Bypass

3.0 Device Operation

When the AVDD pin is pulled low, the reference clock

signal bypasses the PLL and is muxed directly through to

the outputs. The PLL is powered down, and device acts a

fanout buffer. Note that if AVDD is re-established, the

PLL requires a power-up and stabilization time to lock to

the input clock.

The FS61857 precisely aligns the frequency and phase

of the differential HSTL output clocks to the differential

reference input CKP/CKN by use of an on-chip phase-

lock loop (PLL). The PLL generates 10 low-skew, low-

jitter copies of the reference, with the outputs adjusted for

50% duty cycle.

The differential FBOUT clock must be hardwired to the

FBINP/FBINN pins to complete the loop. The PLL ac- 3.2

Power-Down

tively adjusts the output clocks so that there is no phase

error between the reference clock and the feedback in-

put.

Since the device uses a PLL to lock the output clocks to

the input clock, there is a power-up stabilization time that

is required for the PLL to achieve phase lock.

The FS61857 provides an auto power-down feature that

shuts off the PLL and tristates all outputs low if the refer-

ence clock drops below 20MHz. The power-down circuit

is level sensitive, and detects either a DC high or low on

the CKP/CKN input pair. If the input clock rises above

20MHz, the PLL powers back up to re-establish lock.

Note that all inputs and outputs use 2.5V HSTL signal

An asynchronous active-low PWRDWN# signal also

levels.

places the part in the power off state.

ISO9001

QS9000

123 4 5 6 7

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