Datasheet > FS6330

FS6330

更新时间： 2022-11-26 20:48:46

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描述
LAN HUB CLOCK GENERATOR IC

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FS6330 数据手册

FS6330

AMERICAN MICROSYSTEMS, INC.

LAN Hub Clock Generator IC

Preliminary Information

May 2000

Figure 2: Pin Configuration

1.0 Features

•

Develops all the high-speed clocks required for LAN

Hub applications

CLKF

VSS

20 VDD

19 CLKC

18 CLKA

17 VSS

SEL0

X2/REFIN

•

Clock skew on CLKB1:4 clocks < 250ps

Period jitter: 150ps pk-pk typical

16 VDD

Available in 20-pin SSOP and TSSOP packages

VDD

15 CLKB4

14 CLKB3

13 CLKB2

12 VSS

VSS

SEL1

CLKG

VDD 10

11 CLKB1

Figure 1: Block Diagram

CLKA

CLKB1:4

CLKC

CLKF

Crystal

Oscillator

PLL

X2/REFIN

PLL

CLKG

FS6330

Table 1: Frequency Table

FONT

CRYSTAL

SEL1

SEL0

CLKA

CLKB[1:4]

CLKC

CLKF

CLKG

25.000MHz

50.000MHz

66.667MHz

75.000MHz

83.333MHz

100.000MHz

125.000MHz

100.000MHz

125.000MHz

FS6330-01

25MHz

This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.

5.23.00

ISO9001

12 3 4 5 6

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