Datasheet > FM25W256-G

FM25W256-G

更新时间： 2024-03-03 10:10:55

品牌	Logo	应用领域
英飞凌 - INFINEON		存储
页数	文件大小	规格书
22页	1327K
描述
铁电存储器 (F-RAM)

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数据手册

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FM25W256-G 数据手册

FM25W256

the slave responds through the SO pin. Multiple slave devices

may share the SI and SO lines as described earlier.

bit is ‘don’t care’, Cypress recommends that this bit be set to ‘0’

to enable seamless transition to higher memory densities.

The FM25W256 has two separate pins for SI and SO, which can

be connected with the master as shown in Figure 2.

Serial Opcode

After the slave device is selected with CS going LOW, the first

byte received is treated as the opcode for the intended operation.

FM25W256 uses the standard opcodes for memory accesses.

For a microcontroller that has no dedicated SPI bus, a

general-purpose port may be used. To reduce hardware

resources on the controller, it is possible to connect the two data

pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins.

Figure 3 shows such a configuration, which uses only three pins.

Invalid Opcode

If an invalid opcode is received, the opcode is ignored and the

device ignores any additional serial data on the SI pin until the

next falling edge of CS, and the SO pin remains tristated.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the

Most Significant Bit (MSB). This is valid for both address and

data transmission.

Status Register

FM25W256 has an 8-bit Status Register. The bits in the Status

described in Table 3 on page 7.

The 256-Kbit serial F-RAM requires a 2-byte address for any

read or write operation. Because the address is only 15 bits, the

upper bit which is fed in is ignored by the device. Although this

Figure 2. System Configuration with SPI port

SCK

MOSI

MISO

SCK

FM25W256

HOLD WP

SCK

FM25W256

HOLD WP

SI SO

SPI

Microcontroller

C S 1

H O LD 1

W P 1

C S 2

H O LD 2

W P 2

Figure 3. System Configuration without SPI port

P1.0

P1.1

SCK

FM25W256

HOLD WP

SI SO

Microcontroller

P1.2

For both these modes, the input data is latched in on the rising

SPI Modes

edge of SCK starting from the first rising edge after CS goes

active. If the clock starts from a HIGH state (in mode 3), the first

rising edge after the clock toggles is considered. The output data

is available on the falling edge of SCK.

FM25W256 may be driven by a microcontroller with its SPI

peripheral running in either of the following two modes:

■ SPI Mode 0 (CPOL = 0, CPHA = 0)

■ SPI Mode 3 (CPOL = 1, CPHA = 1)

Document Number: 001-84506 Rev. *H

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