Datasheet > FM25V20A-G

FM25V20A-G

更新时间： 2024-03-03 10:08:55

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
33页	678K
描述
2Mb 3.3V Industrial 40MHz SPI F-RAM in 8-pin SOIC

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数据手册

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FM25V20A-G 数据手册

2-Mbit (256K × 8) Serial (SPI) F-RAM

serial (SPI), 256K × 8, 40 MHz, industrial

Functional overview

3.3.3

Chip Select (CS)

To select any slave device, the master needs to pull down the corresponding CS pin. Any instruction can be issued

to a slave device only while the CS pin is LOW. When the device is not selected, data through the SI pin is ignored

and the serial output pin (SO) remains in a high-impedance state.

Note: A new instruction must begin with the falling edge of CS. Therefore, only one opcode can be issued for each

active Chip Select cycle.

3.3.4

Serial Clock (SCK)

The Serial Clock is generated by the SPI master and the communication is synchronized with this clock after CS

goes LOW.

The FM25V20A enables SPI modes 0 and 3 for data communication. In both of these modes, the inputs are latched

by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the first rising

edge of SCK signifies the arrival of the first bit (MSB) of a SPI instruction on the SI pin. Further, all data inputs and

outputs are synchronized with SCK.

3.3.5

Data Transmission (SI/SO)

The SPI data bus consists of two lines, SI and SO, for serial data communication. SI is also referred to as Master

Out Slave In (MOSI) and SO is referred to as Master In Slave Out (MISO). The master issues instructions to the slave

through the SI pin, while the slave responds through the SO pin. Multiple slave devices may share the SI and SO

lines as described earlier.

The FM25V20A has two separate pins for SI and SO, which can be connected with the master as shown in Figure 3.

For a microcontroller that has no dedicated SPI bus, a general-purpose port may be used. To reduce hardware

resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off (HIGH) the WP

pin. Figure 4 shows such a configuration, which uses only three pins.

SCK

MOSI

MISO

SCK

SPI Hostcontroller

SPI Master

FM25V20A

CS1

WP1

CS2

WP2

Figure 3

System Configuration with SPI Port

P1.0

P1.1

SCK

SPI Hostcontroller

FM25V20A

SPI Master

P1.2

Figure 4

System Configuration without SPI Port

Datasheet

001-90261 Rev. *J

2023-12-22

1...4 5 678 9 10...33

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