Datasheet > FM25V20A-G

FM25V20A-G

更新时间： 2024-03-03 10:08:55

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
33页	678K
描述
2Mb 3.3V Industrial 40MHz SPI F-RAM in 8-pin SOIC

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数据手册

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FM25V20A-G 数据手册

2-Mbit (256K × 8) Serial (SPI) F-RAM

serial (SPI), 256K × 8, 40 MHz, industrial

Pin definitions

Table 1

Pin definitions

I/O type

Pin name

Description

Chip Select. This active LOW input activates the device. When HIGH,

the device enters low-power standby mode, ignores other inputs,

and the output is tristated. When LOW, the device internally activates

the SCK signal. A falling edge on CS must occur before every opcode.

Input

Serial Clock. All I/O activity is synchronized to the serial clock. Inputs

are latched on the rising edge and outputs occur on the falling edge.

Because the device is synchronous, the clock frequency may be any

value between 0 MHz and 40 MHz and may be interrupted at any time.

SCK

Serial Input. All data is input to the device on this pin. The pin is

sampled on the rising edge of SCK and is ignored at other times. It

should always be driven to a valid logic level to meet IDD

specifications.

SI^[1]

Input

Serial Output. This is the data output pin. It is driven during a read

and remains tristated at all other times. Data transitions are driven

on the falling edge of the serial clock.

SO^[1]

Output

Write Protect. This Active LOW pin prevents write operation to the

Status Register when WPEN is set to ‘1’. This is critical because other

write protection features are controlled through the Status Register.

A complete explanation of write protection is provided in “Status

V_DDif not used.

Input

DNU

V_SS

Do Not Use

Do Not Use. This pin must be tied to V_DD.

Ground for the device. Must be connected to the ground of the

system.

Power Supply

V_DD

Power supply input to the device.

The EXPOSED PAD on the bottom of 8-pin DFN package is not

connected to the die. The EXPOSED PAD should not be soldered on

the PCB.

EXPOSED PAD

No Connect

Note

1. SI may be connected to SO for a single pin data interface.

Datasheet

001-90261 Rev. *J

2023-12-22

1 2 3 456 7 8...33

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