FM25V02-DG

更新时间： 2024-02-14 19:11:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器光电二极管
页数	文件大小	规格书
18页	504K
描述
256Kb Serial 3V F-RAM Memory

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技术参数
数据手册

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FM25V02-DG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	包装说明：	SOP, SOP8,.25
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.08
Is Samacsys：	N	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
内存密度：	262144 bit	内存集成电路类型：	MEMORY CIRCUIT
内存宽度：	8	混合内存类型：	N/A
湿度敏感等级：	1	功能数量：	1
端子数量：	8	字数：	32768 words
字数代码：	32000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	32KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	2.5/3.3 V
认证状态：	Not Qualified	座面最大高度：	1.75 mm
最大待机电流：	0.00015 A	子类别：	SRAMs
最大压摆率：	0.0025 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	3.9 mm	Base Number Matches：	1

FM25V02-DG 数据手册

FM25V02 - 256Kb SPI FRAM

Protocol Overview

Overview

The SPI interface is a synchronous serial interface

using clock and data pins. It is intended to support

multiple devices on the bus. Each device is activated

using a chip select. Once chip select is activated by

the bus master, the FM25V02 will begin monitoring

the clock and data lines. The relationship between the

falling edge of /S, the clock and data is dictated by

the SPI mode. The device will make a determination

of the SPI mode on the falling edge of each chip

select. While there are four such modes, the

FM25V02 supports only modes 0 and 3. Figure 2

shows the required signal relationships for modes 0

and 3. For both modes, data is clocked into the

FM25V02 on the rising edge of C and data is

expected on the first rising edge after /S goes active.

If the clock starts from a high state, it will fall prior to

the first data transfer in order to create the first rising

edge.

The FM25V02 is a serial F-RAM memory. The

memory array is logically organized as 32,768 x 8

and is accessed using an industry standard Serial

Peripheral Interface or SPI bus. Functional operation

of the F-RAM is similar to Serial Flash. The major

differences between the FM25V02 and a Serial Flash

with the same pinout are the F-RAM‟s superior write

performance, very high endurance, and lower power

consumption.

Memory Architecture

When accessing the FM25V02, the user addresses

32K locations of 8 data bits each. These data bits are

shifted serially. The addresses are accessed using the

SPI protocol, which includes a chip select (to permit

multiple devices on the bus), an op-code, and a two-

byte address. The complete address of 15-bits

specifies each byte address uniquely.

The SPI protocol is controlled by op-codes. These

op-codes specify the commands to the device. After

/S is activated the first byte transferred from the bus

master is the op-code. Following the op-code, any

addresses and data are then transferred.

Most functions of the FM25V02 either are controlled

by the SPI interface or are handled automatically by

on-board circuitry. The access time for memory

operation is essentially zero, beyond the time needed

for the serial protocol. That is, the memory is read or

written at the speed of the SPI bus. Unlike Serial

Flash, it is not necessary to poll the device for a ready

condition since writes occur at bus speed. So, by the

time a new bus transaction can be shifted into the

device, a write operation will be complete. This is

explained in more detail in the interface section.

Certain op-codes are commands with no subsequent

data transfer. The /S must go inactive after an

operation is complete and before a new op-code can

be issued. There is one valid op-code only per active

chip select.

SPI Mode 0: CPOL=0, CPHA=0

Users expect several obvious system benefits from

the FM25V02 due to its fast write cycle and high

endurance as compared to Serial Flash. In addition

there are less obvious benefits as well. For example

in a high noise environment, the fast-write operation

is less susceptible to corruption than Serial Flash

since it is completed quickly. By contrast, Serial

Flash requiring milliseconds to write is vulnerable to

noise during much of the cycle.

MSB

LSB

Serial Peripheral Interface – SPI Bus

SPI Mode 3: CPOL=1, CPHA=1

The FM25V02 employs a Serial Peripheral Interface

(SPI) bus. It is specified to operate at speeds up to

40MHz. This high-speed serial bus provides high

performance serial communication to

host

microcontroller. Many common microcontrollers

have hardware SPI ports allowing a direct interface.

It is quite simple to emulate the port using ordinary

port pins for microcontrollers that do not. The

FM25V02 operates in SPI Mode 0 and 3.

MSB

LSB

Figure 2. SPI Modes 0 & 3

Page 3 of 18

Document Number: 001-84494 Rev. **

1 234 5 6 7...18

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与FM25V02-DG相关器件

型号	品牌	描述	获取价格	数据表
FM25V02-DGTR	CYPRESS	256Kb Serial 3V F-RAM Memory	获取价格
FM25V02-DGTR	RAMTRON	256Kb Serial 3V F-RAM Memory	获取价格
FM25V02-G	CYPRESS	256Kb Serial 3V F-RAM Memory	获取价格
FM25V02-G	RAMTRON	256Kb Serial 3V F-RAM Memory	获取价格
FM25V02-GTR	CYPRESS	256Kb Serial 3V F-RAM Memory	获取价格
FM25V02-GTR	RAMTRON	256Kb Serial 3V F-RAM Memory	获取价格

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