FM25V02-DG

更新时间： 2024-02-20 01:38:01

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器光电二极管
页数	文件大小	规格书
18页	504K
描述
256Kb Serial 3V F-RAM Memory

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技术参数
数据手册

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FM25V02-DG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	包装说明：	SOP, SOP8,.25
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.08
Is Samacsys：	N	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
内存密度：	262144 bit	内存集成电路类型：	MEMORY CIRCUIT
内存宽度：	8	混合内存类型：	N/A
湿度敏感等级：	1	功能数量：	1
端子数量：	8	字数：	32768 words
字数代码：	32000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	32KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	2.5/3.3 V
认证状态：	Not Qualified	座面最大高度：	1.75 mm
最大待机电流：	0.00015 A	子类别：	SRAMs
最大压摆率：	0.0025 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	3.9 mm	Base Number Matches：	1

FM25V02-DG 数据手册

FM25V02 - 256Kb SPI FRAM

BP0 bits are set to 1, the WPEN bit is set to 1, and

the /W pin is low. This occurs because the block

protect bits prevent writing memory and the /W

signal in hardware prevents altering the block protect

bits (if WPEN is high). Therefore in this condition,

hardware must be involved in allowing a write

operation. The following table summarizes the write

protection conditions.

Table 4. Write Protection

WEL

WPEN

Protected Blocks

Protected

Unprotected Blocks

Protected

Unprotected

Status Register

Protected

Unprotected

Protected

Unprotected

read out for each. Addresses are incremented

internally as long as the bus master continues to issue

clocks. If the last address of 7FFFh is reached, the

counter will roll over to 0000h. Data is read MSB

first. The rising edge of /S terminates a READ op-

code operation and tri-states the Q pin. A read

operation is shown in Figure 10.

Memory Operation

The SPI interface, which is capable of a relatively

high clock frequency, highlights the fast write

capability of the F-RAM technology. Unlike Serial

Flash, the FM25V02 can perform sequential writes at

bus speed. No page buffer is needed and any number

of sequential writes may be performed.

Fast Read Operation

Write Operation

The FM25V02 supports the FAST READ op-code

(0Bh) that is found on Serial Flash devices. It is

implemented for code compatibility with Serial Flash

devices. Following this instruction is a two-byte

address (A14-A0), specifying the address of the first

data byte of the read operation. A dummy byte

follows the address. It inserts one byte of read

latency. The D pin is ignored after the op-code, 2-

byte address, and dummy byte are complete. The bus

master issues 8 clocks, with one bit read out for each.

The Fast Read operation is otherwise the same as an

ordinary READ. If the last address of 7FFFh is

reached, the counter will roll over to 0000h. Data is

read MSB first. The rising edge of /S terminates a

FAST READ op-code operation and tri-states the Q

pin. A Fast Read operation is shown in Figure 11.

All writes to the memory array begin with a WREN

op-code. The next op-code is the WRITE instruction.

This op-code is followed by a two-byte address

value, which specifies the 15-bit address of the first

data byte of the write operation. Subsequent bytes are

data and they are written sequentially. Addresses are

incremented internally as long as the bus master

continues to issue clocks. If the last address of 7FFFh

is reached, the counter will roll over to 0000h. Data is

written MSB first. A write operation is shown in

Figure 9.

Unlike Serial Flash, any number of bytes can be

written sequentially and each byte is written to

memory immediately after it is clocked in (after the

8^thclock). The rising edge of /S terminates a WRITE

op-code operation. Asserting /W active in the middle

of a write operation will have no effect until the next

falling edge of /S.

Hold

The FM25V02 and FM25VN02 device has a /HOLD

pin that can be used to interrupt a serial operation

without aborting it. If the bus master pulls the

/HOLD pin low while C is low, the current operation

will pause. Taking the /HOLD pin high while C is

low will resume an operation. The transitions of

/HOLD must occur while C is low, but the C and /S

pins can toggle during a hold state.

Read Operation

After the falling edge of /S, the bus master can issue

a READ op-code. Following this instruction is a two-

byte address value (A14-A0), specifying the address

of the first data byte of the read operation. After the

op-code and address are complete, the D pin is

ignored. The bus master issues 8 clocks, with one bit

Document Number: 001-84494 Rev. **

Page 7 of 18

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与FM25V02-DG相关器件

型号	品牌	描述	获取价格	数据表
FM25V02-DGTR	CYPRESS	256Kb Serial 3V F-RAM Memory	获取价格
FM25V02-DGTR	RAMTRON	256Kb Serial 3V F-RAM Memory	获取价格
FM25V02-G	CYPRESS	256Kb Serial 3V F-RAM Memory	获取价格
FM25V02-G	RAMTRON	256Kb Serial 3V F-RAM Memory	获取价格
FM25V02-GTR	CYPRESS	256Kb Serial 3V F-RAM Memory	获取价格
FM25V02-GTR	RAMTRON	256Kb Serial 3V F-RAM Memory	获取价格

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