Standard Voltage 4.5 ≤ VCC ≤ 5.5V Specifications
Operating Conditions
Absolute Maximum Ratings (Note 1)
Ambient Operating Temperature
FM25C160U
Ambient Storage Temperature
-65°C to +150°C
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltage with
Respect to Ground
FM25C160UE
FM25C160UV
+6.5V to -0.3V
+300°C
Lead Temp. (Soldering, 10 sec.)
ESD Rating
Power Supply (VCC
)
4.5V to 5.5V
2000V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V (unless otherwise specified)
Symbol
Parameter
Conditions
Min
Max
Units
ICC
ICCSB
IIL
Operating Current
/CS = VIL
3
50
mA
µA
µA
µA
V
Standby Current
/CS = VCC
Input Leakage
VIN = 0 to VCC
VOUT = GND to VCC
-1
-1
+1
IOL
Output Leakage
+1
VIL
CMOS Input Low Voltage
CMOS Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
-0.3
VCC * 0.3
VCC + 0.3
0.4
VIH
VOL
VOH
fOP
0.7 * VCC
V
IOL = 1.6 mA
IOH = -0.8 mA
V
VCC - 0.8
V
2.1
2.0
2.0
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tRI
Input Rise Time
tFI
Input Fall Time
tCLH
tCLL
tCSH
tCSS
tDIS
tHDS
tCSN
tDIN
tHDN
tPD
Clock High Time
Clock Low Time
(Note 2)
(Note 2)
(Note 3)
190
190
240
240
100
90
Min /CS High Time
/CS Setup Time
Data Setup Time
/HOLD Setup Time
/CS Hold Time
240
100
90
Data Hold Time
/HOLD Hold Time
Output Delay
CL = 200 pF
240
tDH
Output Hold Time
/HOLD to Output Low Z
Output Disable Time
/HOLD to Output High Z
Write Cycle Time
0
tLZ
100
240
100
10
tDF
CL = 200 pF
tHZ
tWP
1–16 Bytes
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 4)
AC Test Conditions
Output Load
CL = 200 pF
Symbol
COUT
Test
Typ Max Units
Input Pulse Levels
0.1 * VCC – 0.9 * VCC
Output Capacitance
Input Capacitance
3
2
8
6
pF
pF
Timing Measurement Reference Level 0.3 * VCC - 0.7 * VCC
CIN
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, for a fOP of 2.1MHz, the period equals 476ns. In this case if t CLH = is set to 190ns, then tCLL must be set to a minimum of 286ns.
Note 3: /CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 4: This parameter is periodically sampled and not 100% tested.
3
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FM25C160U Rev. B