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FM25C160ULZEN PDF预览

FM25C160ULZEN

更新时间: 2024-01-25 04:49:02
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
11页 104K
描述
SERIAL EEPROM|2KX8|CMOS|DIP|8PIN|PLASTIC

FM25C160ULZEN 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Contact Manufacturer零件包装代码:DIP
包装说明:DIP,针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.8
最大时钟频率 (fCLK):2.1 MHzJESD-30 代码:R-PDIP-T8
JESD-609代码:e0长度:9.817 mm
内存密度:16384 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:8字数:2048 words
字数代码:2000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX8封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:SERIAL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:5.08 mm串行总线类型:SPI
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
最长写入周期时间 (tWC):10 msBase Number Matches:1

FM25C160ULZEN 数据手册

 浏览型号FM25C160ULZEN的Datasheet PDF文件第4页浏览型号FM25C160ULZEN的Datasheet PDF文件第5页浏览型号FM25C160ULZEN的Datasheet PDF文件第6页浏览型号FM25C160ULZEN的Datasheet PDF文件第8页浏览型号FM25C160ULZEN的Datasheet PDF文件第9页浏览型号FM25C160ULZEN的Datasheet PDF文件第10页 
SPI Modes 0 and 3 (00 and 11)  
Functional Description (Continued)  
FM25C160U supports both Mode 0 and Mode 3 of operations.  
The difference between Mode 0 and Mode 3 is determined by the  
state of the SCK clock signal when a SPI cycle starts (when /CS  
is driven low) as well as when the SPI cycle ends (when /CS is  
drivenhigh).UnderMode0ofoperation,theSCKsignalisheldlow  
both at the start and at the end of a SPI cycle. Under Mode 1 of  
operation, the SCK signal is held high both at the start and at the  
end of a SPI cycle. However in both of these two modes, the input  
data(SI)issampled(latchedin)attherisingedgeoftheSCKclock  
signal and the output data (SO) is driven after the falling edge of  
the SCK clock signal. See Figure 1 and Figure 2.  
SPI communication  
As mentioned before, serial communication with the EEPROM is  
enabled when the /CS pin is held low and the /HOLD pin is held  
high. Input data (Instruction Opcodes, Array addresses and Data)  
on the SI pin is latched in on the rising edges of SCK clock signal,  
startingfromthefirstrisingedgeafterthe/CSpingoeslow. During  
the time the SI data is input into the EEPROM, the SO pin remains  
in high impedance state. If the intended instruction is of read  
nature (Array read and Status register read), then data from the  
EEPROM is driven out actively on the SO pin from every falling  
edge of the SCK after the last input data (SI) is latched in. During  
the time the SO data is output from the EEPROM, the data on the  
SI pin is ignored. Figure 2 illustrates the above. Refer Figure 1 for  
timing information.  
READ SEQUENCE (READ)  
Reading the memory via the serial SPI link requires the following  
sequence. The/CS pin is pulled low to select the EEPROM. The  
READ opcode is transmitted on the SI pin followed by two bytes of  
address, "High byte addr" (A15-A8) and "Low byte addr" (A7-A0).  
After this is done, data on the SI pin becomes don't care. The data  
(D7-D0)formtheaddressspecifiedisthenshiftedoutontheSOpin.  
If only one byte is to be read, the /CS pin can be pulled back to the  
high level. It is possible to continue the READ sequence as the byte  
address is automatically incremented and data will continue to be  
shifted out as clock pulses are continuously applied. When the end  
ofmemoryarrayisreached(lastbytelocation),theaddresscounter  
rolls over to the start of memory array (first byte location) allowing  
the entire memory to be read in one continuous READ cycle. See  
Figure 5. Note that only A10-A0 address bits are treated valid by  
FM25C160U while bits A15-A11 are ignored.  
HOLD function  
An active communication with the EEPROM can be temporarily  
suspended by bringing the /HOLD pin low when a EEPROM is  
selected (/CS pin should be low) and a serial sequence with the  
EEPROM is currently underway. To suspend the communication,  
/HOLDpinmustbedrivenlowwhileSCKislow,otherwisetheHold  
function will not be invoked until the next SCK high to low  
transition. The EEPROM must remain selected during this se-  
quence. TransitionsontheSCKandSIpinsareignoredduringthe  
time the part is suspended and the SO pin will be in high  
impedance state. Releasing the /HOLD pin back to high state will  
allow the operation to resume from the point it was suspended.  
/HOLD pin must be driven high while the SCK pin is low, otherwise  
serial communication will not resume until the next SCK high to  
low transition. Asserting a low on the /HOLD pin at any time will tri-  
state the SO pin. Figure 3 illustrates Hold timing.  
FIGURE 5. Read Sequence  
CS  
Read  
Opcode  
High Byte  
Addr  
Low Byte  
Addr  
SI  
System Configuration  
WhenmultipleSPIperipherals(fore.g.EEPROMs)arepresenton  
the bus, the SI, SO and the SCK signals can be tied together.  
Figure 4 illustrates a typical system configuration with respect to  
/CS, SCK, SI and SO pins.  
Data  
(1)  
Data  
(2)  
Data  
(n)  
SO  
READ STATUS REGISTER (RDSR):  
The Read Status Register (RDSR) instruction provides read  
access to the status register. As mentioned before, of the 8bits of  
data, only the LSB 4bits are valid and they indicate Block Protec-  
tion information (BP1 and BP0), Write Enable status (WEN) and  
Busy/Ready status (/RDY) of the EEPROM. MSB 4bits of are  
invalid (Dont cares) Following is the format of RDSR data:  
FIGURE 4. System Configuration  
MASTER MCU  
FM25Cxxx  
DATA OUT (MOSI)  
SI  
DATA IN (MISO)  
SO  
SERIAL CLOCK (SPICK)  
SCK  
TABLE 3. Status Register Format  
SS0  
SS1  
SS2  
SS3  
/CS  
Bit  
7
Bit  
6
Bit  
5
Bit  
4
Bit  
3
Bit  
2
Bit  
1
Bit  
0
SPI  
SI  
SO  
SCK  
/CS  
CHIP  
SELECTION  
X
X
X
X
BP1  
BP0 WEN RDY  
Bit3 (BP1) and Bit2 (BP0) together indicate Block write protection  
previously set on the EEPROM. Refer Table 2.  
SI  
Bit1 (WEN) indicates the Write enable status of the EEPROM.  
This bit is a read-only bit and is read by executing RDSR  
instruction. If this bit is 1then the EEPROM is write enabled. If  
this bit is 0then the EEPROM is write disabled.  
SO  
SCK  
/CS  
SI  
SO  
SCK  
/CS  
7
www.fairchildsemi.com  
FM25C160U Rev. B  

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