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FM25C640ULN PDF预览

FM25C640ULN

更新时间: 2024-02-11 13:20:11
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
11页 103K
描述
EEPROM, 8KX8, Serial, CMOS, PDIP8, PLASTIC, DIP-8

FM25C640ULN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:PLASTIC, DIP-8
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.8最大时钟频率 (fCLK):1 MHz
数据保留时间-最小值:40耐久性:1000000 Write/Erase Cycles
JESD-30 代码:R-PDIP-T8JESD-609代码:e0
长度:9.817 mm内存密度:65536 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:8
字数:8192 words字数代码:8000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8KX8
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:SERIAL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/5 V
认证状态:Not Qualified座面最大高度:5.08 mm
串行总线类型:SPI最大待机电流:0.00001 A
子类别:EEPROMs最大压摆率:0.003 mA
最大供电电压 (Vsup):4.5 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
最长写入周期时间 (tWC):15 ms写保护:HARDWARE/SOFTWARE
Base Number Matches:1

FM25C640ULN 数据手册

 浏览型号FM25C640ULN的Datasheet PDF文件第2页浏览型号FM25C640ULN的Datasheet PDF文件第3页浏览型号FM25C640ULN的Datasheet PDF文件第4页浏览型号FM25C640ULN的Datasheet PDF文件第5页浏览型号FM25C640ULN的Datasheet PDF文件第6页浏览型号FM25C640ULN的Datasheet PDF文件第7页 
February 2002  
FM25C640U  
64K-Bit SPI™ Interface  
Serial CMOS EEPROM  
General Description  
Functions  
The FM25C640U is a 64K bit serial interface CMOS EEPROM  
(Electrically Erasable Programmable Read-Only Memory). This  
device fully conforms to the SPI 4-wire protocol which uses Chip  
Select (/CS), Clock (SCK), Data-in (SI) and Data-out (SO) pins to  
synchronouslycontroldatatransferbetweentheSPImicrocontroller  
andtheEEPROM.Inaddition,theserialinterfaceallowsaminimal  
pin count, packaging designed to simplify PC board layout re-  
quirementsandoffersthedesigneravarietyoflowvoltageandlow  
power options.  
I SPI MODE 0 interface  
I 64K bits organized as 8K x 8  
I Extended 2.7V to 5.5V operating voltage  
I 2.1 MHz operation @ 4.5V - 5.5V  
I Self-timed programming cycle  
I "Programming complete" indicated by STATUS REGISTER  
polling  
I /WP pin and BLOCK WRITE protection  
This SPI EEPROM family is designed to work with the 68HC11 or  
any other SPI-compatible, high-speed microcontroller and offers  
both hardware (/WP pin) and software ("block write") data protec-  
tion. For example, entering a 2-bit code into the STATUS REGIS-  
TER prevents programming in a selected block of memory and all  
Features  
I Sequential read of entire array  
I 32 byte "Page write" mode to minimize total write time per  
byte  
programming can be inhibited by connecting the /WP pin to VSS  
;
allowing the user to protect the entire array or a selected section.  
In addition, SPI devices feature a /HOLD pin, which allows a  
temporary interruption of the datastream into the EEPROM.  
I /WP pin and BLOCK WRITE protection to prevent inadvert-  
ent programming as well as programming ENABLE and  
DISABLE opcodes.  
I /HOLD pin to suspend data transfer  
Fairchild EEPROMs are designed and tested for applications  
requiring high endurance, high reliability, and low power con-  
sumption for a continuously reliable non-volatile solution for all  
markets.  
I Typical 1µA standby current (ISB) for "L" devices and 0.1µA  
standby current for "LZ" devices.  
I Endurance: Up to 1,000,000 data changes  
I Data retention greater than 40 years  
Block Diagram  
/CS  
/HOLD  
SCK  
VCC  
VSS  
Instruction  
Decoder  
Control Logic  
and Clock  
/WP  
Instruction  
SI  
Generators  
Register  
Program  
Enable  
Address  
Counter/  
Register  
High Voltage  
Generator  
and  
Program  
Timer  
VPP  
Decoder  
EEPROM Array  
Read/Write Amps  
Data In/Out Register  
8 Bits  
Data Out  
Buffer  
SO  
Non-Volatile  
Status Register  
SPI™ is a trademark of Motorola Corporation  
1
© 2002 Fairchild Semiconductor Corporation  
FM25C640U Rev. B  
www.fairchildsemi.com  

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