October 1990
FGA Series ASPECTTM ECL Gate Arrays
General Description
The FGA Series is a new generation of ECL gate arrays
based on National’s ASPECT process. These advanced
ECL gate arrays, ranging from 200 to over 30,000 equiva-
lent gates, offer typical internal propagation delays of
150 ps and consume thirty percent less power than conven-
tional ECL arrays. (Refer to Table I.)
All FGA Series products interface with ECL 100K, ECL 10K
and ECL 10KH components, and, except for the FGA200,
FGA14000, FGA14040R, and FGA30000, are fully FAST
/
É
TTL compatible. The TTL interface eliminates requirements
for separate off-chip signal converters in mixed logic level
systems, thereby resulting in reduced board space and cost,
as well as avoiding the performance and reliability penalties
associated with off-chip signal converters.
With system clock frequencies up to 1.2 GHz, the speed
domain of Gallium Arsenide, FGA Series gate arrays are
especially well-suited for such high-performance applica-
tions as mainframe and supermini computers, fiber-optic
communications, and many military and aerospace systems.
In addition to providing superior speed/power performance
with high density, the ASPECT process is scalable to sub-
micron dimensions. FGA Series arrays are designed to ac-
commodate multiple ASPECT process generations to allow
designs implemented today to migrate to tomorrow’s arrays
based on future ASPECT processes.
With only internal cells and I/O cells, FGA Series arrays are
easy to use. Designers can implement logic using two-level
or three-level series gating circuit structures within an array,
with no complex signal mixing rules required. An extensive
macro library, common to all FGA Series arrays, contains
more than eighty SSI/MSI logic functions and 36 supporting
I/O macros. In addition, internal macros may be grouped to
form re-usable ‘‘soft macros’’ with even greater functional
complexity.
Features
Y
New generation ECL gate arrays with complexity to
30,000 equivalent logic gates
Y
Manufactured with 1.5-micron ASPECT process
Y
CAD-programmable speed/power options
All FGA Series gate arrays feature CAD-programmable
speed/power options that allow the designer to maximize
performance by individually assigning the switching speed
and output drive currents for each internal macro. The
speed/power feature provides maximum ECL speed where
needed, yet allows overall chip power to remain at air-coola-
Y
150 ps typical internal delay
Y
Flexible array architecture with only two cell types:
Internal cells and I/O cells
Y
F100K, 10K or 10KH ECL-compatible I/Os
Y
Mixable ECL/TTL I/Os
Y
Allows large number of simultaneously switching
outputs
b
ble levels. On-chip termination to 2V for the internal out-
put emitter followers further reduces power consumption.
TL/U/10560–1
FIGURE 1. FGA Series Gate Array
Note 1: FGA150, 600, 1300, 4000 and 15000 offer mixable ECL/TTL I/Os.
FASTÉ is a registered trademark of National Semiconductor Corporation.
ASPECTTM is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/U/10560
RRD-B30M115/Printed in U. S. A.