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FAN3228T

更新时间： 2024-01-24 06:01:04
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器栅极栅极驱动
页数 文件大小 规格书
12页 459K
描述
Application Review and Comparative Evaluation of Low-Side Gate Drivers

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FAN3228T 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：GREEN, SOIC-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.31.00.01风险等级：5.81
内置保护：TRANSIENT接口集成电路类型：FULL BRIDGE BASED PERIPHERAL DRIVER
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：5 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：125 °C最低工作温度：-40 °C
输出电流流向：SOURCE AND SINK标称输出峰值电流：3 A
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：12 V认证状态：Not Qualified
座面最大高度：1.75 mm子类别：MOSFET Drivers
最大供电电压：18 V最小供电电压：4.5 V
标称供电电压：12 V表面贴装：YES
温度等级：AUTOMOTIVE端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
断开时间：0.022 µs接通时间：0.017 µs
宽度：4 mm

FAN3228T 数据手册

 浏览型号FAN3228T的Datasheet PDF文件第5页浏览型号FAN3228T的Datasheet PDF文件第6页浏览型号FAN3228T的Datasheet PDF文件第7页浏览型号FAN3228T的Datasheet PDF文件第9页浏览型号FAN3228T的Datasheet PDF文件第10页浏览型号FAN3228T的Datasheet PDF文件第11页 
AN-6069  
APPLICATION NOTE  
according to specific circuit layout and ground structure,  
reference [6] gives an approximate value of 10nH/inch  
(4nH/cm) for microstrip on FR-4 with the trace exposed to  
air on one side. This provides an estimate that can be used  
with the circuit capacitance to calculate a damping resistor  
when needed.  
It is difficult to compare competing devices using only  
datasheets, which offer information produced using different  
test conditions. Competing technologies used in integrated  
circuit solutions further complicate device comparison. In  
the following paragraphs, several circuits that can be used to  
test and compare drivers on the bench are presented.  
Figure 19 shows a circuit that can be used to test the pulsed  
current source capability of a driver by clamping VOUT to a  
level equal to VDSCH + VDZEN when the output is high. To  
minimize power dissipation, the input is driven with a 200ns  
positive-going pulse (for non-inverting driver) with a 2%  
duty cycle. In this circuit, the positive-going voltage across  
Figure 17. Compound Driver Output Stage  
R
CS is used to monitor the current sourced out of the driver.  
For compound drivers, the output current is often specified  
with the output voltage at a specified voltage, such as VDD/2,  
to highlight the current that is available during the Miller  
plateau region of the VGS waveform. In tests performed  
using the methods described in section “Evaluating Drivers  
on the Bench” below, the peak output current is generally  
higher than the current specified at VDD/2. Figure 18 shows  
the sink current capability of a 4A compound driver  
(FAN3224C) to be 4.76A, while the output is at 6.1V after  
reaching a peak just under 6A. A compound driver rated at  
4A might deliver a higher peak current than a comparably  
rated PMOS/NMOS driver. This type of information is  
practically impossible to obtain from the driver datasheets,  
so specific test methods are required.  
To change the value of the output clamping voltage, the  
voltage rating of DZEN must be changed.  
VDD  
DSCH  
VPULSE  
VOUT  
CBYP  
DZEN  
+
VCS  
RCS  
-
INPUT at 10V/div  
Figure 19. Current Source Test Circuit with  
Clamped VOUT  
Figure 20 shows a circuit used to test the pulsed current sink  
capability of a driver with the output voltage clamped at a  
level VADJ-VDSCH. Here, the input is driven with a 200ns  
negative-going pulse (for a non-inverting driver) with a 2%  
duty cycle. In this circuit, the negative-going voltage across  
IOUT at 2A/div  
V
OUT at 5V/div  
Time = 200ns/div  
RCS is used to monitor the current that the driver is sinking.  
Figure 18. Compound Driver Current Sink Waveform  
Evaluating Drivers on the Bench  
Real-world driver comparisons are difficult to perform in the  
lab because the fast signal ramp rates cause complex  
interactions between the inductive and capacitive circuit  
components. These fast edge rates can introduce overshoots  
and undershoots of several volts. Some examples to help  
quantify this effect in power circuits can be found in  
reference [5]. Although the parasitic inductance varies  
Figure 20. Current Sink Test Circuit with Clamped VOUT  
© 2007 Fairchild Semiconductor Corporation  
Rev. 1.0.3 • 1/6/10  
www.fairchildsemi.com  
8
1...56789101112

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