AN-6069
APPLICATION NOTE
The PMOS/NMOS version shown in Figure 15 has a natural
inversion and would require an inverter to follow the PWM
signal polarity. This circuit offers rail-to-rail operation, but
shoot-through is a problem that must be considered in design
because both devices can conduct when the common gate
node voltage is in the middle part of the VDD range.
Common methods used for driver datasheet current ratings:
•
•
•
•
Peak current available from device, usually at initial
turn on at maximum VDD
Current available with the output clamped at a specific
voltage, often around VDD/2
Current available with low value resistance to rails
(perhaps 0.5Ω, even short circuit)
Current measured with a current probe
Integrated MOSFET drivers are commonly available in one
of three technologies: primarily MOSFET, bipolar, or a
combination of the two, often referred to as “compound”
devices. The MOSFET and bipolar versions are similar to
the discrete solutions previously mentioned, while the
compound design combines features from both technologies.
For low-side drivers built with a MOS output state (PMOS
high side and NMOS low side, similar to the discrete circuit
illustrated in Figure 15), the datasheet current rating is
generally specified as the peak current available from the
part, often specified with VDD near the maximum rating of
the part. Figure 16 shows the output current and voltage for
a 4A driver using test methods detailed in the section
“Evaluating Drivers on the Bench” below. This testing
shows that the internal circuitry limits the peak output
current to a value near the rated 4A with no external resistor.
Figure 15. Discrete PMOS/NMOS Drive Circuit
Using the discrete driver approach leads to a higher
component count that requires more PCB board space and
more assembly and test time. The higher component count
can lead to more procurement costs and reliability concerns.
If the input signal comes from a logic circuit or a low-
voltage PWM, the discrete driver requires additional
circuitry to translate from logic levels to power drive levels.
Integrated circuit drivers offer significant benefits in
addition to large pulse current capability. New integrated
dual drivers in 3x3mm packages and single drivers in
2x2mm packages include a thermal pad for heat removal.
These devices require less board space than discrete
solutions, while offering enhanced thermal performance, so
they are well-suited for the most dense power designs.
Features integrated into the device, such as an enable
function and UVLO, create ease of use and reduce
component-level design. It has been common practice to
offer drivers with TTL-compatible input thresholds that can
accept inputs ranging from logic-level signals up to the VDD
range of the device. Drivers utilizing CMOS input
thresholds (2/3 VDD = high, 1/3VDD = low) can help alleviate
noise issues or set more accurate timing delays at the input
of the driver.
Figure 16. PMOS/NMOS Driver VOUT and IOUT
The PMOS/NMOS drivers usually specify the driver output
resistance when it is sinking or sourcing a specified current,
such as 100mA. It is interesting to note that the MOS-type
driver does not attain the RO,high or RO,low resistance values
immediately when the device begins switching. For
example, 4A drivers commonly specify a value for RO,high or
RO,low from 1 – 2Ω. If the devices reached this low resistance
value instantaneously, the peak currents would be more than
7A with VDD = 15V.
Driver Datasheet Current Ratings
Driver datasheet current ratings and test conditions can lead
to confusion. Many consider the gate driver to be a near
ideal voltage source that can instantly deliver current as
determined by the circuit series resistance. This is not
necessarily true. Usually, the current available from a driver
is limited by the internal circuit design, regardless of the
semiconductor technology used. This self-limiting nature
should not be confused with self-protecting; if a driver
output is shorted high or low, the device is likely to fail.
In compound devices, bipolar and MOSFET devices are
combined in a parallel configuration, such as the one shown
in Figure 17, where the power output devices are shaded.
The bipolar transistors are able to deliver high sink and
source current, while the output voltage swings through the
middle of the output range. The PMOS and NMOS operate
in parallel with the bipolar devices to pull the output voltage
to the positive or negative rail as required.
© 2007 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/6/10
www.fairchildsemi.com
7
5秒后页面跳转
NTC热敏电阻与PTC热敏电阻的应用原理及应用范围
GTO与普通晶闸管相比为什么可以自关断？为什么普通晶闸管不能呢？从GTO原理、应用范围带你了解原因及推荐型号
LF353数据手册解读：特性、应用、封装、引脚说明、电气参数及替换型号推荐
A4950资料手册解读：特性、应用、封装、引脚功能、电气参数及代换型号
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
