Datasheet > F0448

F0448

更新时间： 2022-06-24 15:40:17

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
35页	3665K
描述
Dual Matched Broadband RF DVGA 3.4GHz to 3.8GHz

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F0448 数据手册

F0448 Datasheet

Electrical Characteristics

See F0448 Typical Application Circuit. V_CC= +5V, T_C= +25°C, f_RF= 3.6GHz specifications apply when operated as a dual-channel RF DVGA,

maximum gain setting, P_OUT= 0dBm, Z_RFI= Z_RFO= 50Ω, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise

stated.

Table 4.

Electrical Characteristics

Parameter

Symbol

V_IH

Condition

Applies for all logic levels.

Minimum

Typical

Maximum

Units

Logic Input High

Logic Input Low

1.07 ^[a]

V_IL

0.63

Logic Current

(CLK, DATA, CSb_A, CSb_B,

VCTRL0_A, VCTRL1_A, VCTRL2_A,

VCTRL0_B, VCTRL1_B, VCTRL2_B)

I_IH,I_IL

-5

μA

5V logic

-5

127

Logic Current for Standby

(STBY_A, STBY_B) ^[b]

_IH-SB,I_IL-SB3.3V logic

1.8V logic

I_{CC_2}

I_{CC_1}

Both channels on

220

110

270

142

Supply Current

Startup Time

One channel on

Standby Mode

I_{CC_STBY}

50% of STBY going LOW to Gain

within ± 1dB with no attenuation.

t_START

DSA0 Adjustment Range

DSA1 Adjustment Range

DSA2 Adjustment Range

Maximum Attenuation Glitch

A_ADJ0

A_ADJ1

6dB step size

1dB step size

6dB step size

A_ADJ2

ATTN_G

50% CTRL to within 0.1dB final value,

0dB state to 6dB state

t_{DSA0_1}

DSA0 Gain Settling Time

DSA1 Gain Settling Time

DSA2 Gain Settling Time

50% CTRL to within 0.1dB final value,

6dB state to 0dB state

t_{DSA0_2}

t_DSA1

300

50% of CSb to within 0.1dB final value

50% CTRL to within 0.1dB final value,

0dB state to 18dB state

t_{DSA2_1}

50% CTRL to within 0.1dB final value,

18dB state to 0dB state

t_{DSA2_2}

50% CTRL to within 1 degree of final

value, 0dB state to 6dB state

t_{DSA0_1_PH}

t_{DSA0_2_PH}

DSA0 Phase Settling Time

50% CTRL to within 1 degree of final

value, 6dB state to 0dB state

October 24, 2018

1...5 6 789 10 11...35

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