F0448 Datasheet
Pin Descriptions
Table 1.
Pin Descriptions
Number
Name
Description
1
RFIN_A
GND
Input RF port for channel A which is internally matched to 50Ω. Must use external DC block.
2, 8, 15, 16,
17, 29, 30, 31
Internally grounded. This pin must be grounded with a via as close to the pin as possible.
1-bit DSA0 6dB attenuator control for channel A. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB
attenuated.
3
VCTRL0_A
4
DATA
CLK
VCC
Data input: 3.3V or 1.8V CMOS compatible.
5
Clock input: 3.3V or 1.8V CMOS compatible.
6, 21, 23, 25
Power Supply. Use bypass capacitors as close to pin as possible.
1-bit DSA0 6dB attenuator control for channel B. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB
attenuated.
7
9
VCTRL0_B
RFIN_B
NC
Input RF port for channel B that is internally matched to 50Ω. Must use external DC block.
10, 18, 20, 26,
28, 36
No internal connection. These pins can be left unconnected or be connected to ground (recommended). Use a via as
close to the pin as possible if grounded.
11
12
CSb_B
STBY_B
Chip Select bar input for channel B: 3.3V or 1.8V CMOS compatible. Logic LOW allows data to be shifted in.
Standby pin for channel B (LOW/Open = device power ON, HIGH = device power OFF with SPI still powered ON). An
internal pull-down resistor of 57kΩ connects between this pin and GND.
13
14
19
22
24
27
32
33
VCTRL1_B
VCTRL2_B
RFOUT_B
RDSET
Bit 0 for DSA2 channel B attenuator. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB attenuated.
Bit 1 for DSA2 channel B attenuator. Logic HIGH is for 12dB attenuated and logic LOW is for 0dB attenuated.
Output RF port for channel B. Use external DC block as close to the pin as possible.
Connect external resistor to GND to optimize amplifier bias. Used with pin 24.
RSET
Connect external resistor to GND to optimize amplifier bias. Used with pin 22.
RFOUT_A
VCTRL2_A
VCTRL1_A
Output RF port for channel A. Use external DC block as close to the pin as possible.
Bit 1 for DSA2 channel A attenuator. Logic HIGH is for 12dB attenuated and logic LOW is for 0dB attenuated.
Bit 0 for DSA2 channel A attenuator. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB attenuated.
Standby pin for channel A (LOW/Open = device power ON, HIGH = device power OFF with SPI still powered ON). An
internal pull-down resistor of 57kΩ connects between this pin and GND.
34
35
STBY_A
CSb_A
Chip Select bar input for channel A: 3.3V or 1.8V CMOS compatible. Logic LOW allows data to be shifted in.
Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board (PCB) pad that
uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground
vias are also required to achieve the specified RF performance.
— EPAD
© 2018 Integrated Device Technology, Inc.
6
October 24, 2018
5秒后页面跳转
MAX6675资料手册参数详解、引脚配置说明
LM258引脚图及功能介绍、主要参数分析
CD4052资料手册参数详解、引脚配置说明
一文带你了解TPS5430资料手册分析：参数介绍、引脚配置说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
