Datasheet > F0448NBGK

F0448NBGK

更新时间： 2024-12-02 02:51:15

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
35页	3665K
描述
Dual Matched Broadband RF DVGA 3.4GHz to 3.8GHz

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F0448NBGK 数据手册

Dual Matched Broadband RF DVGA

3.4GHz to 3.8GHz

F0448

Datasheet

Description

Features

The F0448 is a 3.4GHz to 3.8GHz dual RF digital variable gain

amplifier (DVGA) designed for use in receivers.

RF Frequency Range: 3.4GHz to 3.8GHz

Dual Channel RF amp and DSAs for Diversity / MIMO

Receivers

This dual RF DVGA provides two independent receiver channels

each with 13dB typical maximum gain and 6dB noise figure

designed to operate with a single +5V supply. For each channel,

gain control is split into three separate attenuators: DSA0, a single

6dB step using a single control pin; DSA1, a 23dB SPI-controlled

gain adjustment in 1dB steps; and DSA2, includes 18dB

attenuation in 6dB steps controlled using two control pins. The

F0448 offers +37dBm nominal output IP3 using 220mA total I_CC.

< 2dB overshoot between DSA transitions

13dB typical maximum gain at 3.6GHz

DSA0: Single 6dB coarse step

DSA1: 23dB total gain range in 1dB steps

DSA2: 18dB gain range in 6dB steps

+37dBm OIP3 at 3.6GHz

6dB Noise figure at 3.6GHz

+5V Supply voltage

This device is packaged in a 6 × 6 mm, 36-QFN with 50Ω single-

ended RF input and RF output impedances for ease of integration

into the signal-channel lineup for each of the two channels.

I_CC= 220mA

Independent standby: 7mA standby current

SPI interface for DSA1

Competitive Advantage

1-bit control for DSA0

High reliability

2-bit control for DSA2

High linearity

50Ω input and output impedance

Internally matched

Low DC current

Zero Distortion^TMtechnology

GlitchFree^TMtechnology

Temperature range: -40°C to +105°C

6 × 6 × 0.75 mm 36-QFN package

Typical Applications

Block Diagram

Multi-mode, Multi-carrier Receivers

PHS/PAS Base Stations

Distributed Antenna Systems

Digital Radio

F0448

DSA0A

DSA1A

23dB

RF AMP A

DSA2A

18dB

RFIN_A

RFOUT_A

DATA

6dB

CSb

CLK

Free ^TM

lit

Glitch

Decode

Logic / Bias

VCTRL0

VCTRL1

VCTRL2

6dB

23dB

18dB

STBY

Zero

Distortion

RFIN_B

RFOUT_B

DSA0B

DSA1B

RF AMP B

DSA2B

October 24, 2018

12 3 4 5 6 7...35

中文翻译

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