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EX64-PCS49A PDF预览

EX64-PCS49A

更新时间: 2024-11-07 14:50:07
品牌 Logo 应用领域
ACTEL 可编程逻辑
页数 文件大小 规格书
48页 371K
描述
Field Programmable Gate Array, 3000 Gates, CMOS, PBGA49, 0.8 MM PITCH, CSP-49

EX64-PCS49A 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:0.8 MM PITCH, CSP-49Reach Compliance Code:compliant
风险等级:5.88其他特性:2000 TYPICAL GATES AVAILABLE
CLB-Max的组合延迟:0.7 nsJESD-30 代码:S-PBGA-B49
JESD-609代码:e0长度:7 mm
湿度敏感等级:2等效关口数量:3000
端子数量:49最高工作温度:125 °C
最低工作温度:-40 °C组织:3000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):225可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:1.5 mm
最大供电电压:2.7 V最小供电电压:2.3 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:TIN LEAD SILVER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:7 mm
Base Number Matches:1

EX64-PCS49A 数据手册

 浏览型号EX64-PCS49A的Datasheet PDF文件第2页浏览型号EX64-PCS49A的Datasheet PDF文件第3页浏览型号EX64-PCS49A的Datasheet PDF文件第4页浏览型号EX64-PCS49A的Datasheet PDF文件第5页浏览型号EX64-PCS49A的Datasheet PDF文件第6页浏览型号EX64-PCS49A的Datasheet PDF文件第7页 
v4.2  
eX Family FPGAs  
FuseLock  
Live on Power-Up  
No Power-Up/Down Sequence Required for Supply  
Voltages  
Leading Edge Performance  
240 MHz System Performance  
350 MHz Internal Performance  
3.9 ns Clock-to-Out (Pad-to-Pad)  
Configurable Weak-Resistor Pull-Up or Pull-Down  
for Tristated Outputs during Power-Up  
Individual Output Slew Rate Control  
2.5V, 3.3V, and 5.0V Mixed-Voltage Operation  
with 5.0V Input Tolerance and 5.0V Drive Strength  
Software Design Support with Actel Designer and  
Libero™ Integrated Design Environment (IDE)  
Tools  
Specifications  
3,000 to 12,000 Available System Gates  
Maximum 512 Flip-Flops (Using CC Macros)  
0.22µm CMOS Process Technology  
Up to 100% Resource Utilization with 100% Pin  
Locking  
Up to 132 User-Programmable I/O Pins  
Deterministic Timing  
Unique In-System Diagnostic and Verification  
Capability with Silicon Explorer II  
Boundary Scan Testing in Compliance with IEEE  
Standard 1149.1 (JTAG)  
Fuselock™ Secure Programming Technology  
Prevents Reverse Engineering and Design Theft  
Features  
High-Performance, Low-Power Antifuse FPGA  
LP/Sleep Mode for Additional Power Savings  
Advanced Small-Footprint Packages  
Hot-Swap Compliant I/Os  
Single-Chip Solution  
Nonvolatile  
Product Profile  
De vice  
e X64  
e X128  
e X256  
Capacity  
3,000  
2,000  
6,000  
4,000  
12,000  
8,000  
System Gates  
Typical Gates  
Register Cells  
Dedicated Flip-Flops  
Maximum Flip-Flops  
64  
128  
128  
256  
256  
512  
Combinatorial Cells  
Maximum User I/Os  
128  
84  
256  
100  
512  
132  
Global Clocks  
Hardwired  
Routed  
1
2
1
2
1
2
Speed Grades  
F, Std, –P  
C, I, A  
F, Std, –P  
C, I, A  
F, Std, –P  
C, I, A  
Temperature Grades*  
Package (by pin count)  
TQFP  
64, 100  
49, 128  
64, 100  
49, 128  
100  
128, 180  
CSP  
Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.  
Ju n e 2004  
i
© 2004 Actel Corporation  

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Field Programmable Gate Array