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EX64-PTQ100I PDF预览

EX64-PTQ100I

更新时间: 2024-11-07 06:58:23
品牌 Logo 应用领域
ACTEL 现场可编程门阵列可编程逻辑时钟
页数 文件大小 规格书
49页 410K
描述
eX Family FPGAs

EX64-PTQ100I 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:0.50 MM PITCH, PLASTIC, TQFP-100Reach Compliance Code:compliant
风险等级:5.88Is Samacsys:N
其他特性:ALSO REQUIRES 2.5V OR 3.3V OR 5V SUPPLY最大时钟频率:357 MHz
CLB-Max的组合延迟:0.7 nsJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
湿度敏感等级:3可配置逻辑块数量:128
等效关口数量:3000输入次数:53
逻辑单元数量:192输出次数:53
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C组织:128 CLBS, 3000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):225
电源:2.5,2.5/5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Field Programmable Gate Arrays最大供电电压:2.7 V
最小供电电压:2.3 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

EX64-PTQ100I 数据手册

 浏览型号EX64-PTQ100I的Datasheet PDF文件第2页浏览型号EX64-PTQ100I的Datasheet PDF文件第3页浏览型号EX64-PTQ100I的Datasheet PDF文件第4页浏览型号EX64-PTQ100I的Datasheet PDF文件第5页浏览型号EX64-PTQ100I的Datasheet PDF文件第6页浏览型号EX64-PTQ100I的Datasheet PDF文件第7页 
v4.3  
eX Family FPGAs  
FuseLock  
Live on Power-Up  
No Power-Up/Down Sequence Required for Supply  
Voltages  
Leading Edge Performance  
240 MHz System Performance  
350 MHz Internal Performance  
3.9 ns Clock-to-Out (Pad-to-Pad)  
Configurable Weak-Resistor Pull-Up or Pull-Down  
for Tristated Outputs during Power-Up  
Individual Output Slew Rate Control  
2.5 V, 3.3 V, and 5.0 V Mixed-Voltage Operation  
with 5.0V Input Tolerance and 5.0V Drive Strength  
Software Design Support with Actel Designer and  
Libero™ Integrated Design Environment (IDE)  
Tools  
Specifications  
3,000 to 12,000 Available System Gates  
Maximum 512 Flip-Flops (Using CC Macros)  
0.22µm CMOS Process Technology  
Up to 132 User-Programmable I/O Pins  
Up to 100% Resource Utilization with 100% Pin  
Locking  
Deterministic Timing  
Unique In-System Diagnostic and Verification  
Capability with Silicon Explorer II  
Boundary Scan Testing in Compliance with IEEE  
Standard 1149.1 (JTAG)  
Fuselock™ Secure Programming Technology  
Prevents Reverse Engineering and Design Theft  
Features  
High-Performance, Low-Power Antifuse FPGA  
LP/Sleep Mode for Additional Power Savings  
Advanced Small-Footprint Packages  
Hot-Swap Compliant I/Os  
Single-Chip Solution  
Nonvolatile  
Product Profile  
Device  
eX64  
eX128  
eX256  
Capacity  
3,000  
2,000  
6,000  
4,000  
12,000  
8,000  
System Gates  
Typical Gates  
Register Cells  
Dedicated Flip-Flops  
Maximum Flip-Flops  
64  
128  
128  
256  
256  
512  
Combinatorial Cells  
Maximum User I/Os  
128  
84  
256  
100  
512  
132  
Global Clocks  
Hardwired  
Routed  
1
2
1
2
1
2
Speed Grades  
F, Std, –P  
C, I, A  
F, Std, –P  
C, I, A  
F, Std, –P  
C, I, A  
Temperature Grades*  
Package (by pin count)  
TQFP  
CSP  
64, 100  
49, 128  
64, 100  
49, 128  
100  
128, 180  
Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.  
June 2006  
i
© 2006 Actel Corporation  

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