Datasheet > EX128-PCSG100PP

EX128-PCSG100PP

更新时间： 2024-11-21 11:54:07

品牌	Logo	应用领域
ACTEL		/
页数	文件大小	规格书
49页	410K
描述
eX Family FPGAs

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中文翻译

获取价格

数据手册

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EX128-PCSG100PP 数据手册

v4.3

eX Family FPGAs

FuseLock

•

Live on Power-Up

No Power-Up/Down Sequence Required for Supply

Voltages

Leading Edge Performance

•

240 MHz System Performance

350 MHz Internal Performance

3.9 ns Clock-to-Out (Pad-to-Pad)

•

Configurable Weak-Resistor Pull-Up or Pull-Down

for Tristated Outputs during Power-Up

Individual Output Slew Rate Control

2.5 V, 3.3 V, and 5.0 V Mixed-Voltage Operation

with 5.0V Input Tolerance and 5.0V Drive Strength

Software Design Support with Actel Designer and

Libero™ Integrated Design Environment (IDE)

Tools

•

Specifications

•

3,000 to 12,000 Available System Gates

Maximum 512 Flip-Flops (Using CC Macros)

0.22µm CMOS Process Technology

Up to 132 User-Programmable I/O Pins

•

Up to 100% Resource Utilization with 100% Pin

Locking

•

Deterministic Timing

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Boundary Scan Testing in Compliance with IEEE

Standard 1149.1 (JTAG)

Fuselock™ Secure Programming Technology

Prevents Reverse Engineering and Design Theft

Features

•

High-Performance, Low-Power Antifuse FPGA

•

LP/Sleep Mode for Additional Power Savings

Advanced Small-Footprint Packages

Hot-Swap Compliant I/Os

Single-Chip Solution

Nonvolatile

Product Profile

Device

eX64

eX128

eX256

Capacity

3,000

2,000

6,000

4,000

12,000

8,000

System Gates

Typical Gates

Dedicated Flip-Flops

Maximum Flip-Flops

128

256

512

Combinatorial Cells

Maximum User I/Os

128

256

100

512

132

Global Clocks

Hardwired

Routed

Speed Grades

–F, Std, –P

C, I, A

–F, Std, –P

C, I, A

–F, Std, –P

C, I, A

Temperature Grades*

Package (by pin count)

TQFP

CSP

64, 100

49, 128

64, 100

49, 128

100

128, 180

Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.

June 2006

12 3 4 5 6 7...49

中文翻译

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