Datasheet > EX128-PTQG100I

EX128-PTQG100I

更新时间： 2024-11-25 21:20:51

品牌	Logo	应用领域
美高森美 - MICROSEMI		时钟栅可编程逻辑
页数	文件大小	规格书
48页	2647K
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中文翻译

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数据手册

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EX128-PTQG100I 数据手册

Revision 10

eX Family FPGAs

•

Single-Chip Solution

Nonvolatile

Leading Edge Performance

•

240 MHz System Performance

350 MHz Internal Performance

3.9 ns Clock-to-Out (Pad-to-Pad)

Live on Power-Up

No Power-Up/Down Sequence Required for Supply

Voltages

•

Configurable Weak-Resistor Pull-Up or Pull-Down for

Tristated Outputs during Power-Up

Specifications

•

Individual Output Slew Rate Control

•

3,000 to 12,000 Available System Gates

2.5 V, 3.3 V, and 5.0 V Mixed-Voltage Operation with

5.0V Input Tolerance and 5.0V Drive Strength

Maximum 512 Flip-Flops (Using CC Macros)

0.22 µm CMOS Process Technology

•

Software Design Support with Microsemi Designer and

Libero^®Integrated Design Environment (IDE) Tools

Up to 132 User-Programmable I/O Pins

•

Up to 100% Resource Utilization with 100% Pin Locking

Deterministic Timing

Features

Unique In-System Diagnostic and Verification Capability

with Silicon Explorer II

•

High-Performance, Low-Power Antifuse FPGA

•

Boundary Scan Testing in Compliance with IEEE

Standard 1149.1 (JTAG)

LP/Sleep Mode for Additional Power Savings

Advanced Small-Footprint Packages

Hot-Swap Compliant I/Os

Fuselock™ Secure Programming Technology Designed

to Prevent Reverse Engineering and Design Theft

Product Profile

Device

eX64

eX128

eX256

Capacity

3,000

2,000

6,000

4,000

12,000

8,000

System Gates

Typical Gates

Dedicated Flip-Flops

Maximum Flip-Flops

128

256

512

Combinatorial Cells

Maximum User I/Os

128

256

100

512

132

Global Clocks

Hardwired

Routed

Speed Grades

–F, Std, –P

C, I, A

–F, Std, –P

C, I, A

–F, Std, –P

C, I, A

Temperature Grades*

Package (by pin count)

64, 100

100

Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.

October 2012

12 3 4 5 6 7...48

中文翻译

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