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ETC5067FN-X PDF预览

ETC5067FN-X

更新时间： 2024-01-29 00:07:29
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解码器编解码器电信集成电路电信电路放大器功率放大器LTEPC
页数 文件大小 规格书
18页 271K
描述
POWER AMPLIFIER SERIAL INTERFACE CODEC/FILTERWITH RECEIVE

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ETC5067FN-X 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：DIP包装说明：PLASTIC, DIP-20
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.84
Is Samacsys：N压伸定律：A-LAW
滤波器：YES最大增益公差：0.15 dB
JESD-30 代码：R-PDIP-T20JESD-609代码：e3
长度：25.15 mm线性编码：NOT AVAILABLE
负电源额定电压：-5 V功能数量：1
端子数量：20工作模式：SYNCHRONOUS/ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP20,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：+-5 V认证状态：Not Qualified
座面最大高度：3.93 mm子类别：Codecs
最大压摆率：12 mA标称供电电压：5 V
表面贴装：NO技术：CMOS
电信集成电路类型：PCM CODEC温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

ETC5067FN-X 数据手册

 浏览型号ETC5067FN-X的Datasheet PDF文件第1页浏览型号ETC5067FN-X的Datasheet PDF文件第2页浏览型号ETC5067FN-X的Datasheet PDF文件第4页浏览型号ETC5067FN-X的Datasheet PDF文件第5页浏览型号ETC5067FN-X的Datasheet PDF文件第6页浏览型号ETC5067FN-X的Datasheet PDF文件第7页 
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X  
PIN DESCRIPTION  
Name  
Pin  
Type (*)  
N
Description  
VPO+  
GNDA  
VPO-  
VPI  
O
GND  
O
1
2
3
4
The Non-inverting Output of the Receive Power Amplifier  
Analog Ground. All signals are referenced to this pin.  
The Inverting Output of the Receive Power Amplifier  
I
Inverting Input to the Receive Power Amplifier. Also powers down both  
amplifiers when connected to VBB  
.
VFRO  
VCC  
O
S
I
5
6
7
Analog Output of the Receive Filter.  
Positive Power Supply Pin. VCC = +5V ±5%  
FSR  
Receive Frame Sync Pulse which enable BCLKR to shift PCM data into  
DR. FSR is an 8KHz pulse train. See figures 1 and 2 for timing details.  
DR  
I
I
8
9
Receive Data Input. PCM data is shifted into DR following the FSR leading  
edge  
BCLKR/CLKSEL  
The bit Clock which shifts data into DR after the FSR leading edge. May  
vary from 64KHz to 2.048MHz.  
Alternatively, may be a logic input which selects either 1.536MHz/1.544MHz  
or 2.048MHz for master clock in synchronous mode and BCLKX is used  
for both transmit and receive directions (see table 1). This input has an  
internal pull-up.  
MCKLR/PDN  
I
10  
Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May  
be asynchronous with MCLKX, but should be synchronous with MCLKX for  
best performance. When MCLKR is connected continuously low, MCLKX is  
selected for all internal timing. When MCLKR is connected continuously  
high, the device is powered down.  
MCLKX  
BCLKX  
I
I
11  
12  
Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May  
be asynchronous with MCLKR.  
The bit clock which shifts out the PCM data on DX. May vary from 64KHz  
to 2.048MHz, but must be synchronous with MCLKX.  
DX  
O
I
13  
14  
The TRI-STATE PCM data output which is enabled by FSX.  
FSX  
Transmit frame sync pulse input which enables BCLKX to shift out the  
PCM data on DX. FSX is an 8KHz pulse train. See figures 1 and 2 for  
timing details.  
TSX  
O
I
15  
16  
Open drain output which pulses low during the encoder time slot. Must to  
be grounded if not used.  
ANLB  
Analog Loopback Control Input. Must be set to logic ’0’ for normal  
operation. When pulled to logic ’1’, the transmit filter input is disconnected  
from the output of the transmit preamplifier and connected to the VPO+  
output of the receive power amplifier.  
GSX  
VFXI-  
VFXI+  
VBB  
O
I
17  
18  
19  
20  
Analog output of the transmit input amplifier. Used to set gain externally.  
Inverting input of the transmit input amplifier.  
I
Non-inverting input of the transmit input amplifier.  
Negative Power Supply Pin. VBB = -5V ±5%  
S
(*) I: Input, O: Output, S: Power Supply.  
TRI-STATE is a trademark of National Semiconductor Corp.  
3/18  
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