ETC5067FN-X

更新时间： 2024-01-08 01:36:44

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		解码器编解码器电信集成电路电信电路放大器功率放大器 LTE PC
页数	文件大小	规格书
18页	271K
描述
POWER AMPLIFIER SERIAL INTERFACE CODEC/FILTERWITH RECEIVE

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ETC5067FN-X 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	PLASTIC, DIP-20
针数：	20	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.84
Is Samacsys：	N	压伸定律：	A-LAW
滤波器：	YES	最大增益公差：	0.15 dB
JESD-30 代码：	R-PDIP-T20	JESD-609代码：	e3
长度：	25.15 mm	线性编码：	NOT AVAILABLE
负电源额定电压：	-5 V	功能数量：	1
端子数量：	20	工作模式：	SYNCHRONOUS/ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	+-5 V	认证状态：	Not Qualified
座面最大高度：	3.93 mm	子类别：	Codecs
最大压摆率：	12 mA	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
电信集成电路类型：	PCM CODEC	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

ETC5067FN-X 数据手册

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

pulses are being used. For 64 kHz operation, the

frame sync pulses must be kept low for a minimum

of 160 ns (see Fig 1). The D_XTRI-STATE output

buffer is enabledwith the rising edge of FS_Xor the

rising edge of BCLK_X, whichever comes later, and

the first bit clocked out is the sign bit. The following

seven BCLK_Xrising edges clock out the remaining

seven bits. The D_Xoutputis disabled by the falling

BCLK_Xedge following the eighth rising edge, or by

FS_Xgoinglow, whichevercomeslater. Arising edge

on thereceive frame sync pulse, FS_R, will cause the

PCM data at D_Rto be latched in on the next eight

falling edges of BCLK_R(BCLK_xin synchronous

mode).Bothdevicesmay utilize the longframe sync

pulse in synchronous or asynchronousmode.

RECEIVE SECTION

The receive section consist of an expanding DAC

which drives a fifth order switched-capacitor low

pass filter clocked at 256kHz. The decoderis A-law

(ETC5067 and ETC5067-X) or µ–law (ETC5064

and ETC5064-X) and the 5 th order low pass filter

corrects for the sin x/x attenuation due to the 8kHz

sample and hold. The filter is then followed by a 2

nd order RC active post-filter and power amplifier

capableof driving a 600Ω load to a levelof 7.2dBm.

The receive section is unity-gain. Upon the oc-

curence of FS_R, the data at the D_Rinput is clocked

in on the falling edge of the next eight BCLK_R

(BCKL_X) periods.At the endofthedecodertime slot,

the decoding cycle begins, and 10µs later the de-

coder DAC outputis updated.Thetotaldecoder de-

lay is about10µs (decoderup-date) plus 110µs (fil-

ter delay) plus 62.5µs (1/2 frame), which gives ap-

proximately 180µs.

TRANSMIT SECTION

The transmitsectioninput isan operationalamplifier

with provision for gainadjustmentusingtwoexternal

resistors,seefigure4. Thelownoiseandwide band-

width allow gains in excess of 20 dB across the

audio passband to be realized. The op amp drives

a unity gain filter consisting of RC active pre-filter,

followed by an eighth order switched-capacitor

bandpass filter directly drives the encodersample-

and-hold circuit. The A/D is of companding type ac-

cording to A-law (ETC5067 and ETC5067-X) or µ-

law (ETC5064 and ETC5064-X) coding conven-

tions. A precision voltage reference is trimmed in

RECEIVE POWER AMPLIFIERS

Two inverting mode power amplifiers are provided

for directly driving a matched line interface trans-

former. The gain of the first power amplifier can be

adjustedto boostthe± 2.5Vpeakoutputsignalfrom

the receive filter up ± 3.3V peak into an unbalanced

300Ω load,or ±4.0V into an unbalanced15kΩ load.

The second power amplifier is internally connected

in unity-gain inverting mode to give 6dB of signal

gainfor balancedloads. Maximumpowertransferto

a 600Ω subscriber line termination is obtained by

differientially driving a balanced transformer with a

√2 : 1 turns ratio, as shown in figure 4. A total peak

power of 15.6dBmcan be delivered to the load plus

termination. Both power amplifier can be powered

downindependentlyfromthe PDNinputbyconnect-

ing the VPI input to V_BBsaving approximately 12

mW of power.

manufacturing to provide an input over load (t_MAX

of nominally 2.5V peak (see table of Transmission

Characteristics). The FS_Xframe sync pulse controls

thesampling of thefileroutput,andthenthesucces-

sive-approximationencodingcyclebegins.The8-bit

code is then loaded into a buffer and shifted out

throughD_Xatthe next FS_Xpulse.the total encoding

delaywill be approximately165µs (due to the trans-

mit filter) plus 125µs (due to encodingdelay), which

totals 290µs. Any offset voltage due to the filters or

comparator is cancelled by sign bit integration.

)

ABSOLUTE MAXIMUM RATINGS

Symbol

V_CC

Parameter

Value

Unit

V_CCto GNDA

V_BBto GNDA

V_BB

-7

V_IN, V_OUTVoltage at any Analog Input or Output

Voltage at any Digital Input or Output

V_CC+0.3 to V_BB-0.3

V_CC+0.3 to GNDA -0.3

T_oper

Operating Temperature Range: ETC5064/67

ETC5064-X/67-X

-25 to +125

-40 to +125

°C

T_stg

Storage Temperature Range

-65 to +150

300

°C

Lead Temperature (soldering, 10 seconds)

5/18

1 2 3 456 7 8...18

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与ETC5067FN-X相关器件

型号	品牌	描述	获取价格	数据表
ETC5067J	ETC	A-Law CODEC	获取价格
ETC5067N	STMICROELECTRONICS	POWER AMPLIFIER SERIAL INTERFACE CODEC/FILTERWITH RECEIVE	获取价格
ETC5067N-X	STMICROELECTRONICS	POWER AMPLIFIER SERIAL INTERFACE CODEC/FILTERWITH RECEIVE	获取价格
ETC5067-X	STMICROELECTRONICS	POWER AMPLIFIER SERIAL INTERFACE CODEC/FILTERWITH RECEIVE	获取价格
ETC50DRAF	ETC	.100 [2.54mm] CONTACT CENTERS, 431 INSULATOR HEIGHT	获取价格
ETC50DRAH	ETC	.100 [2.54mm] CONTACT CENTERS, 431 INSULATOR HEIGHT	获取价格

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