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ETC5054D-X/HTR PDF预览

ETC5054D-X/HTR

更新时间： 2024-10-30 19:47:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS PC电信光电二极管电信集成电路
页数 文件大小 规格书
18页 1552K
描述
MU-LAW, PCM CODEC, PDSO16, SOP-16

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中文翻译

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ETC5054D-X/HTR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP-16
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.83
压伸定律：MU-LAW滤波器：YES
JESD-30 代码：R-PDSO-G16长度：10.3 mm
负电源额定电压：-5 V功能数量：1
端子数量：16工作模式：SYNCHRONOUS/ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
认证状态：Not Qualified座面最大高度：2.65 mm
标称供电电压：5 V表面贴装：YES
技术：CMOS电信集成电路类型：PCM CODEC
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

ETC5054D-X/HTR 数据手册

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ETC5054  
ETC5057  
®
SERIAL INTERFACE CODEC/FILTER  
COMPLETE CODEC AND FILTERING SYS-  
TEM (DEVICE) INCLUDING:  
– Transmit high-pass and low-pass filtering.  
– Receive low-pass filter with sin x/x correction.  
– Active RC noise filters  
– µ-law or A-law compatible COder and DECoder.  
– Internal precision voltage reference.  
– Serial I/O interface.  
– Internal auto-zero circuitry.  
DIP16 (Plastic)  
A-LAW 16 PINS (ETC5057FN, 20 PINS)  
µ-LAW WITHOUT SIGNALING, 16 PINS  
(ETC5054FN, 20 PINS)  
MEETS OR EXCEEDS ALL D3/D4 AND  
CCITT SPECIFICATIONS  
ORDERING NUMBERS:  
ETC5057N  
ETC5054N  
±5V OPERATION  
LOW OPERATING POWER - TYPICALLY 60  
mW  
POWER-DOWN STANDBY MODE - TYPI-  
CALLY 3 mW  
AUTOMATIC POWER-DOWN  
TTL OR CMOS COMPATIBLE DIGITAL IN-  
TERFACES  
SO16 (Wide)  
MAXIMIZES LINE INTERFACE CARD CIR-  
CUIT DENSITY  
0 to 70°C OPERATION  
ORDERING NUMBERS:  
ETC5057D  
ETC5054D  
DESCRIPTION  
The ETC5057/ETC5054 family consists of A-law  
and µ–law monolithic PCM CODEC/filters utilizing  
the A/D and D/A conversion architecture shown in  
the block diagram below, and a serial PCM inter-  
face. The devices are fabricated using double-  
poly CMOS process. The encode portion of each  
device consists of an input gain adjust amplifier,  
an active RC pre-filter which eliminates very high  
frequency noise prior to entering a switched-ca-  
pacitor band-pass filter that rejects signals below  
200 Hz and above 3400 Hz. Also included are  
auto-zero circuitry and a companding coder which  
samples the filtered signal and encodes it in the  
companded A-law or µ–law PCM format. The de-  
code portion of each device consists of an ex-  
panding decoder, which reconstructs the analog  
signal from the companded A-law or µ–law code,  
a low-pass filter which corrects for the sin x/x re-  
sponse of the decoder output and rejects signals  
above 3400 Hz and is followed by a single-ended  
power amplifier capable of driving low impedance  
loads. The devices require 1.536 MHz, 1.544  
PLCC20  
ORDERING NUMBERS:  
ETC5057FN  
ETC5054FN  
MHz, or 2.048 MHz transmit and receive master  
clocks, which may be asynchronous, transmit and  
receive bit clocks which may vary from 64 kHz to  
2.048 MHz, and transmit and receive frame sync  
pulses. The timing of the frame sync pulses and  
PCM data is compatible with both industry stand-  
ard formats.  
March 2000  
1/18  
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.  
1234567...18

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