ETC5054J/G

更新时间： 2024-10-30 13:07:43

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		解码器过滤器编解码器 LTE
页数	文件大小	规格书
18页	155K
描述
IC,PCM CODEC,SINGLE,CMOS,DIP,16PIN,CERAMIC

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技术参数
数据手册

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ETC5054J/G 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	not_compliant	风险等级：	5.87
压伸定律：	MU-LAW	滤波器：	YES
最大增益公差：	0.15 dB	JESD-30 代码：	R-XDIP-T16
JESD-609代码：	e0	线性编码：	NOT AVAILABLE
负电源额定电压：	-5 V	功能数量：	1
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	CERAMIC
封装代码：	DIP	封装等效代码：	DIP16,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
电源：	+-5 V	认证状态：	Not Qualified
子类别：	Codecs	最大压摆率：	9 mA
标称供电电压：	5 V	表面贴装：	NO
技术：	CMOS	电信集成电路类型：	PCM CODEC
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	Base Number Matches：	1

ETC5054J/G 数据手册

ETC5054

ETC5057

SERIAL INTERFACE CODEC/FILTER

COMPLETE CODEC AND FILTERING SYS-

TEM (DEVICE) INCLUDING:

– Transmithigh-pass and low-pass filtering.

– Receivelow-pass filter with sin x/x correction.

– ActiveRC noise filters

– µ-lawor A-lawcompatibleCOderandDECoder.

– Internalprecision voltage reference.

– Serial I/O interface.

– Internalauto-zero circuitry.

DIP16 (Plastic)

A-LAW 16 PINS (ETC5057FN, 20 PINS)

µ-LAW WITHOUT SIGNALING, 16 PINS

(ETC5054FN, 20 PINS)

MEETS OR EXCEEDS ALL D3/D4 AND

CCITT SPECIFICATIONS

ORDERING NUMBERS:

ETC5057N

ETC5054N

5V OPERATION

LOW OPERATING POWER - TYPICALLY 60

POWER-DOWN STANDBY MODE - TYPI-

CALLY 3 mW

AUTOMATIC POWER-DOWN

TTL OR CMOS COMPATIBLE DIGITAL IN-

TERFACES

SO16 (Wide)

MAXIMIZES LINE INTERFACE CARD CIR-

CUIT DENSITY

0 to 70°C OPERATION

ORDERING NUMBERS:

ETC5057D

ETC5054D

DESCRIPTION

The ETC5057/ETC5054 family consists of A-law

and µ–law monolithic PCM CODEC/filters utilizing

the A/D and D/A conversion architecture shown in

the block diagram below, and a serial PCM inter-

face. The devices are fabricated using double-

poly CMOS process. The encode portion of each

device consists of an input gain adjust amplifier,

an active RC pre-filter which eliminates very high

frequency noise prior to entering a switched-ca-

pacitor band-pass filter that rejects signals below

200 Hz and above 3400 Hz. Also included are

auto-zero circuitry and a companding coder which

samples the filtered signal and encodes it in the

PLCC20

ORDERING NUMBERS:

ETC5057FN

ETC5054FN

companded A-law or –law PCM format. The de-

code portion of each device consists of an ex-

panding decoder, which reconstructs the analog

signal from the companded A-law or µ–law code,

a low-pass filter which corrects for the sin x/x re-

sponse of the decoder output and rejects signals

above 3400 Hz and is followed by a single-ended

power amplifier capable of driving low impedance

loads. The devices require 1.536 MHz, 1.544

MHz, or 2.048 MHz transmit and receive master

clocks, which may be asynchronous, transmit and

receive bit clocks which may vary from 64 kHz to

2.048 MHz, and transmit and receive frame sync

pulses. The timing of the frame sync pulses and

PCM data is compatible with both industry stand-

ard formats.

March 2000

1/18

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

12 3 4 5 6 7...18

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与ETC5054J/G相关器件

型号	品牌	获取价格	描述	数据表
ETC5054J-X	ETC	获取价格	u-Law CODEC
ETC5054N	STMICROELECTRONICS	获取价格	SERIAL INTERFACE CODEC/FILTER
ETC5054N-X	STMICROELECTRONICS	获取价格	MU-LAW, PCM CODEC, PDIP16, PLASTIC, DIP-16
ETC5056J	STMICROELECTRONICS	获取价格	IC,PCM CODEC,SINGLE,CMOS,DIP,20PIN,CERAMIC
ETC5057	STMICROELECTRONICS	获取价格	SERIAL INTERFACE CODEC/FILTER
ETC5057D	STMICROELECTRONICS	获取价格	SERIAL INTERFACE CODEC/FILTER
ETC5057D-X	ETC	获取价格	A-Law CODEC
ETC5057FN	ETC	获取价格	A-Law CODEC
ETC5057FN/G	ETC	获取价格	A-Law CODEC
ETC5057FN-X	ETC	获取价格	A-Law CODEC

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