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EPX8160QC208-10 PDF预览

EPX8160QC208-10

更新时间: 2024-02-04 07:09:21
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟输入元件可编程逻辑
页数 文件大小 规格书
44页 615K
描述
Flash PLD, 10ns, CMOS, PQFP208, PLASTIC, QFP-208

EPX8160QC208-10 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:FQFP, QFP208,1.2SQ,20针数:208
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.86
其他特性:CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V最大时钟频率:95.2 MHz
JESD-30 代码:S-PQFP-G208JESD-609代码:e0
长度:28 mm湿度敏感等级:3
专用输入次数:48I/O 线路数量:120
输入次数:172逻辑单元数量:160
输出次数:172端子数量:208
最高工作温度:70 °C最低工作温度:
组织:48 DEDICATED INPUTS, 120 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP208,1.2SQ,20封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH峰值回流温度(摄氏度):220
电源:3.3/5,5 V可编程逻辑类型:FLASH PLD
传播延迟:10 ns认证状态:Not Qualified
座面最大高度:4.1 mm子类别:Field Programmable Gate Arrays
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:28 mm
Base Number Matches:1

EPX8160QC208-10 数据手册

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FLASHlogic  
Programmable Logic  
Device Family  
®
June 1996, ver. 2  
Data Sheet  
High-performance programmable logic device (PLD) family  
Features...  
SRAM-based logic with shadow FLASH memory elements  
fabricated on advanced CMOS technology  
Logic densities from 1,600 to 3,200 usable gates (see Table 1)  
Combinatorial speeds with t as low as 10 ns  
PD  
Counter frequencies of up to 80 MHz  
8 to 16 logic array blocks (LABs) linked by a 100%-connectable  
programmable interconnect array (PIA) for improved fitting of  
complex designs  
24V10 macrocell features available  
Dual feedback on all I/O pins  
Product-term allocation matrix supporting up to 16 product  
terms per macrocell  
Programmable registers providing D, T, SR, and JK flipflop  
functionality with clear, preset, and clock controls  
Fast 12-bit identity compare option  
Fully compliant with PCI Local Bus Specification, version 2.1  
Table 1. FLASHlogic Device Features  
Feature  
EPX880  
EPX8160  
Usable gates  
1,600  
10,240  
80  
3,200  
Maximum SRAM bits  
Macrocells  
20,480  
160  
16  
Logic array blocks (LABs)  
8
Package options  
84-pin PLCC (62)  
208-pin PQFP (172)  
(maximum user I/O pins)  
132-pin PQFP (104)  
t
t
f
(ns)  
(ns)  
10  
6
10  
6
PD  
CO  
(MHz)  
80  
80  
CNT  
Altera Corporation  
265  
A-DS-FLSH-02  

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