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EPM7128ABI256-10 PDF预览

EPM7128ABI256-10

更新时间: 2024-11-01 15:31:55
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟输入元件可编程逻辑
页数 文件大小 规格书
68页 1559K
描述
EE PLD, 10ns, CMOS, PBGA256, BGA-256

EPM7128ABI256-10 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:256
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.56其他特性:128 MACROCELLS
最大时钟频率:125 MHzJESD-30 代码:S-PBGA-B256
JESD-609代码:e1长度:27 mm
专用输入次数:I/O 线路数量:100
端子数量:256最高工作温度:85 °C
最低工作温度:-40 °C组织:0 DEDICATED INPUTS, 100 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY可编程逻辑类型:EE PLD
传播延迟:10 ns认证状态:Not Qualified
座面最大高度:2.3 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:27 mm
Base Number Matches:1

EPM7128ABI256-10 数据手册

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Includes  
MAX 7000AE  
MAX 7000A  
Programmable Logic  
Device Family  
®
June 1999, ver. 2.01  
Data Sheet  
High-performance CMOS EEPROM-based programmable logic  
devices (PLDs) built on second-generation Multiple Array MatriX  
(MAX®) architecture (see Table 1)  
3.3-V in-system programmability (ISP) through the built-in  
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with  
advanced pin-locking capability  
Features...  
Built-in boundary-scan test (BST) circuitry compliant with  
IEEE Std. 1149.1-1990  
Enhanced ISP features  
Preliminary  
Information  
Enhanced ISP algorithm for faster programming (excluding  
EPM7128A and EPM7256A devices)  
ISP_Done bit to ensure complete programming (excluding  
EPM7128A and EPM7256A devices)  
Pull-up resistor on I/O pins during in-system programming  
Pin-compatible with the popular 5.0-V MAX 7000S devices  
High-density PLDs ranging from 600 to 10,000 usable gates  
4.5-ns pin-to-pin logic delays with counter frequencies of up to  
192.3 MHz  
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V  
MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family  
Data Sheet or the MAX 7000B Programmable Logic Device Family Advance  
Information Brief.  
f
Table 1. MAX 7000A Device Features  
Feature  
EPM7032AE  
EPM7064AE  
EPM7128AE  
EPM7128A  
EPM7256AE  
EPM7256A  
EPM7512AE  
Usable gates  
Macrocells  
600  
32  
2
1,250  
64  
2,500  
128  
8
5,000  
256  
16  
10,000  
512  
Logic array blocks  
4
32  
Maximum user I/O  
pins  
36  
68  
100  
164  
212  
t
t
t
t
f
(ns)  
(ns)  
4.5  
3.0  
4.5  
3.0  
5.0  
3.2  
6.0  
3.7  
7.5  
4.9  
PD  
SU  
(ns)  
2.5  
2.5  
2.5  
2.5  
3.0  
FSU  
CO1  
CNT  
(ns)  
2.8  
2.8  
3.0  
3.3  
4.5  
(MHz)  
192.3  
192.3  
181.8  
156.3  
119.0  
Altera Corporation  
595  
A-DS-M7000A-02.01  

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