Datasheet > EPM7128ABC256-6

EPM7128ABC256-6

更新时间： 2024-11-02 08:54:43

品牌	Logo	应用领域
阿尔特拉 - ALTERA		/
页数	文件大小	规格书
68页	1559K
描述
EE PLD, 6ns, CMOS, PBGA256, BGA-256

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EPM7128ABC256-6 数据手册

Includes

MAX 7000AE

MAX 7000A

Programmable Logic

Device Family

June 1999, ver. 2.01

Data Sheet

■

High-performance CMOS EEPROM-based programmable logic

devices (PLDs) built on second-generation Multiple Array MatriX

(MAX^®) architecture (see Table 1)

3.3-V in-system programmability (ISP) through the built-in

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with

advanced pin-locking capability

Features...

■

Built-in boundary-scan test (BST) circuitry compliant with

IEEE Std. 1149.1-1990

Enhanced ISP features

Preliminary

Information

–

Enhanced ISP algorithm for faster programming (excluding

EPM7128A and EPM7256A devices)

ISP_Done bit to ensure complete programming (excluding

EPM7128A and EPM7256A devices)

Pull-up resistor on I/O pins during in-system programming

■

Pin-compatible with the popular 5.0-V MAX 7000S devices

High-density PLDs ranging from 600 to 10,000 usable gates

4.5-ns pin-to-pin logic delays with counter frequencies of up to

192.3 MHz

For information on in-system programmable 5.0-V MAX 7000 or 2.5-V

MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family

Data Sheet or the MAX 7000B Programmable Logic Device Family Advance

Information Brief.

Table 1. MAX 7000A Device Features

Feature

EPM7032AE

EPM7064AE

EPM7128AE

EPM7128A

EPM7256AE

EPM7256A

EPM7512AE

Usable gates

Macrocells

600

1,250

2,500

128

5,000

256

10,000

512

Logic array blocks

Maximum user I/O

pins

100

164

212

(ns)

4.5

3.0

4.5

3.0

5.0

3.2

6.0

3.7

7.5

4.9

(ns)

2.5

3.0

FSU

CO1

CNT

(ns)

2.8

3.0

3.3

4.5

(MHz)

192.3

181.8

156.3

119.0

Altera Corporation

595

A-DS-M7000A-02.01

12 3 4 5 6 7...68

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