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EPM240T100C4 PDF预览

EPM240T100C4

更新时间: 2024-01-13 09:44:03
品牌 Logo 应用领域
阿尔特拉 - ALTERA 可编程逻辑器件输入元件LTE
页数 文件大小 规格书
6页 86K
描述
The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-m

EPM240T100C4 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TFQFP, TQFP100,.63SQReach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:1.19
其他特性:IT CAN ALSO OPERATE AT 3.3V系统内可编程:YES
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
JTAG BST:YES长度:14 mm
湿度敏感等级:3专用输入次数:
I/O 线路数量:80宏单元数:192
端子数量:100最高工作温度:85 °C
最低工作温度:组织:0 DEDICATED INPUTS, 80 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP100,.63SQ
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.5/3.3,2.5/3.3 V
可编程逻辑类型:FLASH PLD传播延迟:6.1 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Programmable Logic Devices最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:MATTE TIN (472) OVER COPPER
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:14 mmBase Number Matches:1

EPM240T100C4 数据手册

 浏览型号EPM240T100C4的Datasheet PDF文件第1页浏览型号EPM240T100C4的Datasheet PDF文件第3页浏览型号EPM240T100C4的Datasheet PDF文件第4页浏览型号EPM240T100C4的Datasheet PDF文件第5页浏览型号EPM240T100C4的Datasheet PDF文件第6页 
1–2  
Chapter 1: Introduction  
Features  
Table 1–1 shows the MAX II family features.  
Table 1–1. MAX II Family Features  
EPM240  
EPM570  
EPM1270  
EPM2210  
Feature  
LEs  
EPM240G  
EPM570G  
EPM1270G  
EPM2210G  
EPM240Z  
EPM570Z  
570  
240  
192  
570  
440  
1,270  
980  
2,210  
1,700  
240  
192  
Typical Equivalent Macrocells  
Equivalent Macrocell Range  
UFM Size (bits)  
Maximum User I/O pins  
tPD1 (ns) (1)  
440  
128 to 240 240 to 570 570 to 1,270 1,270 to 2,210  
128 to 240  
8,192  
80  
240 to 570  
8,192  
160  
8,192  
80  
8,192  
160  
5.4  
8,192  
212  
6.2  
8,192  
272  
7.0  
4.7  
7.5  
9.0  
fCNT (MHz) (2)  
304  
1.7  
304  
1.2  
304  
1.2  
304  
1.2  
152  
152  
tSU (ns)  
2.3  
2.2  
tCO (ns)  
4.3  
4.5  
4.6  
4.6  
6.5  
6.7  
Notes to Table 1–1:  
(1) tPD1 represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and combinational logic  
implemented in a single LUT and LAB that is adjacent to the output pin.  
(2) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay will run faster than this number.  
f
For more information about equivalent macrocells, refer to the MAX II Logic Element to  
Macrocell Conversion Methodology white paper.  
MAX II and MAX IIG devices are available in three speed grades: –3, –4, and –5, with  
–3 being the fastest. Similarly, MAX IIZ devices are available in three speed grades: –6,  
–7, and –8, with –6 being the fastest. These speed grades represent the overall relative  
performance, not any specific timing parameter. For propagation delay timing  
numbers within each speed grade and density, refer to the DC and Switching  
Characteristics chapter in the MAX II Device Handbook.  
Table 1–2 shows MAX II device speed-grade offerings.  
Table 1–2. MAX II Speed Grades  
Speed Grade  
Device  
EPM240  
–3  
–4  
–5  
–6  
–7  
–8  
v
v
v
EPM240G  
EPM570  
v
v
v
v
v
v
v
v
v
EPM570G  
EPM1270  
EPM1270G  
EPM2210  
EPM2210G  
EPM240Z  
EPM570Z  
v
v
v
v
v
v
MAX II Device Handbook  
© August 2009 Altera Corporation  

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