5秒后页面跳转
EPM240T100I5 PDF预览

EPM240T100I5

更新时间: 2024-02-18 05:55:53
品牌 Logo 应用领域
英特尔 - INTEL 输入元件可编程逻辑
页数 文件大小 规格书
88页 982K
描述
Flash PLD, 7.5ns, 192-Cell, CMOS, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100

EPM240T100I5 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:TFQFP, TQFP100,.63SQReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:0.61Samacsys Confidence:4
Samacsys Status:Released2D Presentation:https://componentsearchengine.com/2D/0T/1382972.1.1.png
Schematic Symbol:https://componentsearchengine.com/symbol.php?partID=1382972PCB Footprint:https://componentsearchengine.com/footprint.php?partID=1382972
3D View:https://componentsearchengine.com/viewer/3D.php?partID=1382972Samacsys PartID:1382972
Samacsys Image:https://componentsearchengine.com/Images/9/EPM240T100I5N.jpgSamacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/1/EPM240T100I5N.jpg
Samacsys Pin Count:100Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Quad Flat PackagesSamacsys Footprint Name:5M80ZT100
Samacsys Released Date:2018-11-07 11:55:21Is Samacsys:N
其他特性:IT CAN ALSO OPERATE AT 3.3V系统内可编程:YES
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
JTAG BST:YES长度:14 mm
湿度敏感等级:3专用输入次数:
I/O 线路数量:80宏单元数:192
端子数量:100组织:0 DEDICATED INPUTS, 80 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP100,.63SQ
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.5/3.3,2.5/3.3 V
可编程逻辑类型:FLASH PLD传播延迟:7.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Programmable Logic Devices最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

EPM240T100I5 数据手册

 浏览型号EPM240T100I5的Datasheet PDF文件第2页浏览型号EPM240T100I5的Datasheet PDF文件第3页浏览型号EPM240T100I5的Datasheet PDF文件第4页浏览型号EPM240T100I5的Datasheet PDF文件第5页浏览型号EPM240T100I5的Datasheet PDF文件第6页浏览型号EPM240T100I5的Datasheet PDF文件第7页 
Section I. MAX II Device Family Data  
Sheet  
®
This section provides designers with the data sheet specifications for MAX II devices.  
The chapters contain feature definitions of the internal architecture, Joint Test Action  
Group (JTAG) and in-system programmability (ISP) information, DC operating  
conditions, AC timing parameters, and ordering information for MAX II devices.  
This section includes the following chapters:  
Chapter 1, Introduction  
Chapter 2, MAX II Architecture  
Chapter 3, JTAG and In-System Programmability  
Chapter 4, Hot Socketing and Power-On Reset in MAX II Devices  
Chapter 5, DC and Switching Characteristics  
Chapter 6, Reference and Ordering Information  
Revision History  
Refer to each chapter for its own specific revision history. For information about when  
each chapter was updated, refer to the Chapter Revision Dates section, which appears  
in the complete handbook.  
© August 2009 Altera Corporation  
MAX II Device Handbook  

与EPM240T100I5相关器件

型号 品牌 描述 获取价格 数据表
EPM240T100I5ES INTEL Flash PLD, PQFP100, 16 X 16 MM, 1MM PITCH, TQFP-100

获取价格

EPM240T100I5N ALTERA Flash PLD, 7.5ns, 192-Cell, CMOS, PQFP100, 16 X 16 MM, 0.50 MM PITCH, LEAD FREE, TQFP-100

获取价格

EPM240T100I5N INTEL Flash PLD, 7.5ns, 192-Cell, CMOS, PQFP100, 16 X 16 MM, 0.50 MM PITCH, LEAD FREE, TQFP-100

获取价格

EPM240Z ALTERA MAX II Device Family Data

获取价格

EPM240Z100C5N ALTERA The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-m,

获取价格

EPM240ZF100A ALTERA MAX II Device Family

获取价格