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EPM240T100I5 PDF预览

EPM240T100I5

更新时间: 2024-01-05 13:41:33
品牌 Logo 应用领域
英特尔 - INTEL 输入元件可编程逻辑
页数 文件大小 规格书
88页 982K
描述
Flash PLD, 7.5ns, 192-Cell, CMOS, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100

EPM240T100I5 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:TFQFP, TQFP100,.63SQReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:0.61Samacsys Confidence:4
Samacsys Status:ReleasedSamacsys PartID:1382972
Samacsys Pin Count:100Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Quad Flat PackagesSamacsys Footprint Name:5M80ZT100
Samacsys Released Date:2018-11-07 11:55:21Is Samacsys:N
其他特性:IT CAN ALSO OPERATE AT 3.3V系统内可编程:YES
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
JTAG BST:YES长度:14 mm
湿度敏感等级:3专用输入次数:
I/O 线路数量:80宏单元数:192
端子数量:100组织:0 DEDICATED INPUTS, 80 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP100,.63SQ
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.5/3.3,2.5/3.3 V
可编程逻辑类型:FLASH PLD传播延迟:7.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Programmable Logic Devices最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

EPM240T100I5 数据手册

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Chapter 1: Introduction  
1–3  
Features  
MAX II devices are available in space-saving FineLine BGA, Micro FineLine BGA,  
and thin quad flat pack (TQFP) packages (refer to Table 1–3 and Table 1–4). MAX II  
devices support vertical migration within the same package (for example, you can  
migrate between the EPM570, EPM1270, and EPM2210 devices in the 256-pin  
FineLine BGA package). Vertical migration means that you can migrate to devices  
whose dedicated pins and JTAG pins are the same and power pins are subsets or  
supersets for a given package across device densities. The largest density in any  
package has the highest number of power pins; you must lay out for the largest  
planned density in a package to provide the necessary power pins for migration. For  
I/O pin migration across densities, cross reference the available I/O pins using the  
device pin-outs for all planned densities of a given package type to identify which  
®
I/O pins can be migrated. The Quartus II software can automatically cross-reference  
and place all pins for you when given a device migration list.  
Table 1–3. MAX II Packages and User I/O Pins  
68-Pin  
Micro  
100-Pin  
Micro  
144-Pin  
Micro  
256-Pin  
Micro  
100-Pin  
256-Pin  
324-Pin  
FineLine FineLine FineLine 100-Pin 144-Pin FineLine  
FineLine FineLine FineLine  
Device  
EPM240  
BGA (1)  
BGA (1)  
BGA  
TQFP  
TQFP  
BGA (1)  
BGA (1)  
BGA  
BGA  
80  
80  
80  
EPM240G  
EPM570  
76  
76  
76  
116  
116  
160  
212  
160  
212  
204  
EPM570G  
EPM1270  
EPM1270G  
EPM2210  
EPM2210G  
EPM240Z  
EPM570Z  
Note to Table 1–3:  
272  
54  
80  
76  
116  
160  
(1) Packages available in lead-free versions only.  
Table 1–4. MAX II TQFP, FineLine BGA, and Micro FineLine BGA Package Sizes  
68-Pin  
Micro  
100-Pin  
Micro  
144-Pin  
Micro  
256-Pin  
Micro  
100-Pin  
256-Pin  
324-Pin  
FineLine FineLine FineLine 100-Pin 144-Pin FineLine FineLine FineLine FineLine  
Package  
Pitch (mm)  
Area (mm2)  
BGA  
BGA  
BGA  
TQFP  
TQFP  
BGA  
BGA  
BGA  
BGA  
0.5  
0.5  
1
0.5  
0.5  
0.5  
0.5  
1
1
25  
36  
121  
256  
484  
49  
121  
289  
361  
Length × width  
(mm × mm)  
5 × 5  
6 × 6  
11 × 11  
16 × 16 22 × 22  
7 × 7  
11 × 11  
17 × 17  
19 × 19  
© August 2009 Altera Corporation  
MAX II Device Handbook  

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