Datasheet > EPF10K200SPC240-3

EPF10K200SPC240-3

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
阿尔特拉 - ALTERA		/
页数	文件大小	规格书
120页	1901K
描述
Loadable PLD, 16ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, PLASTIC, QFP-240

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EPF10K200SPC240-3 数据手册

FLEX 10KE Embedded Programmable Logic Family Data Sheet

Each FLEX 10KE device contains an enhanced embedded array to

implement memory and specialized logic functions, and a logic array to

implement general logic.

Functional

Description

The embedded array consists of a series of EABs. When implementing

memory functions, each EAB provides 4,096 bits, which can be used to

create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.

When implementing logic, each EAB can contribute 100 to 600 gates

towards complex logic functions, such as multipliers, microcontrollers,

state machines, and DSP functions. EABs can be used independently, or

multiple EABs can be combined to implement larger functions.

The logic array consists of logic array blocks (LABs). Each LAB contains

eight LEs and a local interconnect. An LE consists of a 4-input look-up

table (LUT), a programmable flipflop, and dedicated signal paths for carry

and cascade functions. The eight LEs can be used to create medium-sized

blocks of logic—such as 8-bit counters, address decoders, or state

machines—or combined across LABs to create larger logic blocks. Each

LAB represents about 96 usable gates of logic.

Signal interconnections within FLEX 10KE devices (as well as to and from

device pins) are provided by the FastTrack Interconnect routing structure,

which is a series of fast, continuous row and column channels that run the

entire length and width of the device.

Each I/O pin is fed by an I/O element (IOE) located at the end of each row

and column of the FastTrack Interconnect routing structure. Each IOE

contains a bidirectional I/O buffer and a flipflop that can be used as either

an output or input register to feed input, output, or bidirectional signals.

When used with a dedicated clock pin, these registers provide exceptional

performance. As inputs, they provide setup times as low as 0.9 ns and

hold times of 0 ns. As outputs, these registers provide clock-to-output

times as low as 3.6 ns. IOEs provide a variety of features, such as JTAG

BST support, slew-rate control, tri-state buffers, and open-drain outputs.

Altera Corporation

1...5 6 789 10 11...120

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型号	品牌	描述	获取价格	数据表
EPF10K200SPI240-2	ALTERA	Loadable PLD, 12ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, PLASTIC, QFP-240	获取价格
EPF10K200SRC240-1	ALTERA	Loadable PLD, 0.3ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240	获取价格
EPF10K200SRC240-1N	ALTERA	Loadable PLD, 0.3ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240	获取价格
EPF10K200SRC240-1X	ETC	Field Programmable Gate Array (FPGA)	获取价格
EPF10K200SRC240-2	ALTERA	Loadable PLD, 0.6ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240	获取价格
EPF10K200SRC240-2N	ALTERA	Loadable PLD, 0.6ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240	获取价格