Datasheet > EPF10K200SPC240-3

EPF10K200SPC240-3

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
阿尔特拉 - ALTERA		/
页数	文件大小	规格书
120页	1901K
描述
Loadable PLD, 16ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, PLASTIC, QFP-240

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EPF10K200SPC240-3 数据手册

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FLEX 10KE Embedded Programmable Logic Family Data Sheet

Figure 1 shows a block diagram of the FLEX 10KE architecture. Each

group of LEs is combined into an LAB; groups of LABs are arranged into

rows and columns. Each row also contains a single EAB. The LABs and

EABs are interconnected by the FastTrack Interconnect routing structure.

IOEs are located at the end of each row and column of the FastTrack

Interconnect routing structure.

Figure 1. FLEX 10KE Device Block Diagram

Embedded Array Block (EAB)

I/O Element

(IOE)

IOE

IOE IOE

IOE

IOE IOE IOE IOE

IOE

Column

Interconnect

Logic Array

EAB

Logic Array

Block (LAB)

IOE

Logic Element (LE)

Row

Interconnect

EAB

Local Interconnect

Logic

Array

IOE

IOE IOE

IOE

Embedded Array

FLEX 10KE devices provide six dedicated inputs that drive the flipflops’

control inputs and ensure the efficient distribution of high-speed, low-

skew (less than 1.5 ns) control signals. These signals use dedicated routing

channels that provide shorter delays and lower skews than the FastTrack

Interconnect routing structure. Four of the dedicated inputs drive four

global signals. These four global signals can also be driven by internal

logic, providing an ideal solution for a clock divider or an internally

generated asynchronous clear signal that clears many registers in the

device.

Altera Corporation

1...6 7 8910 11 12...120

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与EPF10K200SPC240-3相关器件

型号	品牌	获取价格	描述	数据表
EPF10K200SPI240-2	ALTERA	获取价格	Loadable PLD, 12ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, PLASTIC, QFP-240
EPF10K200SRC240-1	ALTERA	获取价格	Loadable PLD, 0.3ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240
EPF10K200SRC240-1N	ALTERA	获取价格	Loadable PLD, 0.3ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240
EPF10K200SRC240-1X	ETC	获取价格	Field Programmable Gate Array (FPGA)
EPF10K200SRC240-2	ALTERA	获取价格	Loadable PLD, 0.6ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240
EPF10K200SRC240-2N	ALTERA	获取价格	Loadable PLD, 0.6ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240
EPF10K200SRC240-2X	ALTERA	获取价格	Loadable PLD, 0.6ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240
EPF10K200SRC240-3	ALTERA	获取价格	Loadable PLD, 0.8ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240
EPF10K200SRC240-3N	ALTERA	获取价格	Loadable PLD, 0.8ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240
EPF10K20BC356-4	ALTERA	获取价格	Loadable PLD, 23.8ns, CMOS, PBGA356, HEAT SINK, BGA-356