He
epc701/epc703
Absolute Maximum Ratings (Note 1)
Recommended Operating Conditions
Min.
9.6
Max.
30
Units
V
Power Supply Voltage VDD
-0.3 to +36.0 V (Note 2)
Power Supply Voltage (VDD)
maximum Power Dissipation
Storage Temperature Range (TS)
100mW
-40°C to +85°C
Operating Temperature (TO)
Humidity (non-condensing)
-40°
+5
+85°
+95
C
Lead Temperature solder, 4 sec. (TL) +260°C
%
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended operating conditions indi-
cate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifica-
tions and test conditions, see Electrical Characteristics.
Note 2: Supply voltages up to 36 Volts may be present for 10 seconds only.
Note 3: This device is a highly sensitive CMOS amplifier with an ESD rating of JEDEC HBM class 1C (>1kV). Handling and assembly of this
device should only be done at ESD protected workstations.
Electrical Characteristics
VDD = 9.6V < VDD < 30V, -40°C < TA < +85°C
Symbol
Parameter
Conditions/Comments
Values
Typ.
Units
Min.
Max.
30
VDD
Supply Voltage
9.6
V
%VDD
μA
V
ΔVDD Ripple on Supply Voltage
Peak-Peak
no load
10
IDD
Supply Current
Output Voltage
300
400
30
VOUT
VSat
ISENS
0
Output Saturation Voltage @50mA output current referenced to VDD
-1
60
-2
V
Sens Current
Current trigger threshold
50
70
mA
V
VSENS Current Sens Voltage
Over-current trigger threshold voltage (by using an external
power switch), referenced to VDD
-0.18
-0.2
-0.25
IPeak
Short Circuit Peak Current Initial current during a short circuit (<1ms, 50Ω series resist-
or)
-0.6
A
V
VStatus Status Output (referenced Logical high
2
5.5
0.8
-12
1.9
5.5
0.8
to GND)
Logical low
-0.3
-8
Sink driving capability
epc703 only, duty cycle 50%
Input (referenced to GND) Logical high
-10
1.7
mA
Hz
fStatus Status Output Frequency
1.5
2.0
-0.3
0.25
100
VIN
Logical low
V
Hysteresis
Pull-down resistance
150
200
100
1.2
kΩ
mW
μs
PDIS
tON
Power Dissipation
Response Time
Response Time
Off-delay Time
On-chip power dissipation
On
Off
1.0
0.7
tOFF
tdel
1.0
μs
Time between over-current detection and STATUS/OUT
change (default value), refer to section Programming
40.0
50.0
60.0
μs
Programmable off-delay values
5/10/20/50/100/200/500/1,000
400 500 600
tminOFF Recovery Time
Minimum down time of the OUT pin to protect the external
transistor (default value), refer to section Programming
ms
Programmable values
10/20/50/100/200/500/1,000/
1,500
frt
Short circuit recovery
delay time factor
tminoff/tdelay = frt (when used without external driver transistor,
refer to section “Over-current Reset Sequence”)
1,000
tSTARTUP Start-up time
VDD ramp > 100 V/ms
200
μs
nF
CL_max External Load Capacit-
ance
Load capacitance that can be driven through OUT without trig -
gering over-current @2kOhm load and 5μs delay time
30
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
2
Datasheet epc701_703 - V2.2
www.espros.ch
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