SMD 14 Pin 5 Tap TTL
Compatible Active Delay Lines
Delays are ±5% or ±2 nS
SMD Part
Number
Delays are ±5% or ±2 nS
SMD Part
Number
Tap
Total
Tap
Total
80, 160, 240, 320
84, 168, 252, 336
88, 176, 264, 352
90, 180, 270, 360
94, 188, 282, 376
100, 200, 300, 400
110, 220, 330, 440
120, 240, 360, 480
130, 260, 390, 520
140, 280, 420, 560
150, 300, 450, 600
160, 320, 480, 640
170, 340, 510, 680
180, 360, 540, 720
190, 380, 570, 760
200, 400, 600, 800
400
420
440
450
470
500
550
600
650
700
750
800
850
900
950
1000
EPA2398-400
EPA2398-420
EPA2398-440
EPA2398-450
EPA2398-470
EPA2398-500
EPA2398-550
EPA2398-600
EPA2398-650
EPA2398-700
EPA2398-750
EPA2398-800
EPA2398-850
EPA2398-900
EPA2398-950
EPA2398-1000
5, 10, 15, 20
6, 12, 18, 24
7, 14, 21, 28
8, 16, 24, 32
25
30
35
40
45
50
60
75
100
125
150
175
200
225
250
300
350
EPA2398-25
EPA2398-30
EPA2398-35
EPA2398-40
EPA2398-45
EPA2398-50
EPA2398-60
EPA2398-75
EPA2398-100
EPA2398-125
EPA2398-150
EPA2398-175
EPA2398-200
EPA2398-225
EPA2398-250
EPA2398-300
EPA2398-350
9, 18, 27, 36
10, 20, 30, 40
12, 24, 36, 48
15, 30, 45, 60
20, 40, 60, 80
25, 50, 75, 100
30, 60, 90, 120
35, 70, 105, 140
40, 80, 120, 160
45, 90, 135, 180
50, 100, 150, 200
60, 120, 180, 240
70, 140, 210, 280
Delay times referenced from input to leading edges at 25°C, 5.0V, with no load.
DC Electrical Characteristics
Schematic
Parameter
Test Conditions
Min Max Unit
V
High-Level Output Voltage
Low-Level Output Voltage
Input Clamp Voltage
V
= min. V = max. I = max 2.7
OH
V
V
V
µA
mA
mA
mA
OH
CC
IL
V
V
= min. V = min. I = max
0.5
-1.2
50
1.0
-2
OL
CC IH OL
14
12
10
6
8
VCC
4
OUTPUT
V
I
V
= min. I = II
K
IK
CC
I
High-Level Input Current
V
= max. V = 2.7V
IH
CC
IN
V
CC
= max. V = 5.25V
IN
INPUT 1
I
Low-Level Input Current
Short Circuit Output Current
V
= max. V = 0.5V
IL
CC IN
I
V
= max. V
= 0.
-40
-100
OS
CC OUT
(One output at a time)
7
GROUND
I
High-Level Supply Current
Low-Level Supply Current
Output Rise Time
V
= max. V = OPEN
75
75
4
mA
mA
nS
CCH
CC
IN
= max. V = 0
I
V
CCL
CC
IN
T
Td £ 500 nS (0.75 to 2.4 Volts)
RO
Td > 500 nS
5
nS
N
N
L
Fanout High-Level Output
Fanout Low-Level Output
V
= max. V = 2.7V
= max. V = 0.5V
20 TTL LOAD
10 TTL LOAD
H
CC
OH
V
CC OL
Recommended
Operating Conditions
Package
Min Max Unit
V
Supply Voltage
4.75
2.0
V
V
V
mA
mA
mA
%
%
°C
5.25
CC
V
High-Level Input Voltage
Low-Level Input Voltage
Input Clamp Current
High-Level Output Current
Low-Level Output Current
Pulse Width of Total Delay
Duty Cycle
IH
V
0.8
-18
-1.0
20
IL
IK
OH
I
I
I
.200
OL
P
*
40
0
W
d*
T
40
+70
PCA
EPA2398-25
Suggested Solder
Pad Layout
.055
.430
.420
Max.
.280
Max.
Operating Free-Air Temperature
A
Date Code
*These two values are inter-dependent.
.300
.200
.300
.03
Input Pulse Test Conditions @ 25° C
Unit
.780 Max.
E
Pulse Input Voltage
3.2
Volts
%
nS
MHz
KHz
Volts
IN
.01
Typ.
P
Pulse Width % of Total Delay
Pulse Rise Time (0.75 - 2.4 Volts)
Pulse Repetition Rate @ Td £ 200 nS
Pulse Repetition Rate @ Td > 200 nS
Supply Voltage
50
2.0
W
.200
Max.
T
RI
P
5.0
100
5.0
RR
.02
.100
.050
.300
V
CC
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
FAX: (818) 894-5791
E L E C T R O N I C S I N C .
EPA2398 10/92