Datasheet > EP4SE230F29C2N

EP4SE230F29C2N

更新时间： 2024-11-05 14:37:55

品牌	Logo	应用领域
阿尔特拉 - ALTERA		时钟 LTE PC 栅可编程逻辑
页数	文件大小	规格书
22页	496K
描述
Field Programmable Gate Array, 9120 CLBs, 800MHz, 228000-Cell, CMOS, PBGA780, 29 X 29 MM, LEAD FREE, FBGA-780

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EP4SE230F29C2N 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	BGA
包装说明：	29 X 29 MM, LEAD FREE, FBGA-780	针数：	780
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.29	Samacsys Confidence：	3
Samacsys Status：	Released	Samacsys PartID：	7284888
Samacsys Pin Count：	780	Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	BGA	Samacsys Footprint Name：	780-Pin FineLine Ball-Grid Array (FBGA) - Flip Chip - Channel Lid - A:3.40
Samacsys Released Date：	2020-05-15 03:13:14	Is Samacsys：	N
最大时钟频率：	800 MHz	JESD-30 代码：	S-PBGA-B780
JESD-609代码：	e1	长度：	29 mm
湿度敏感等级：	4	可配置逻辑块数量：	9120
输入次数：	488	逻辑单元数量：	228000
输出次数：	488	端子数量：	780
最高工作温度：	85 °C	最低工作温度：
组织：	9120 CLBS	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA780,28X28,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	245	电源：	0.9,1.2/3,1.5,2.5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	3.4 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	0.93 V	最小供电电压：	0.87 V
标称供电电压：	0.9 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40	宽度：	29 mm
Base Number Matches：	1

EP4SE230F29C2N 数据手册

1. Overview for the Stratix IV Device

Family

January 2016

SIV51001-3.5

Altera^®Stratix^®IV FPGAs deliver a breakthrough level of system bandwidth and

power efficiency for high-end applications, allowing you to innovate without

compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor

Manufacturing Company (TSMC) 40-nm process technology and surpass all other

high-end FPGAs, with the highest logic density, most transceivers, and lowest power

requirements.

The Stratix IV device family contains three optimized variants to meet different

application requirements:

■

Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 kilobits

(Kb) RAM, and 1,288 18 x 18 bit multipliers

■

Stratix IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kb RAM, 1,288

18 x 18-bit multipliers, and 48 full-duplex clock data recovery (CDR)-based

transceivers at up to 8.5 Gbps

■

Stratix IV GT—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers,

and 48 full-duplex CDR-based transceivers at up to 11.3 Gbps

The complete Altera high-end solution includes the lowest risk, lowest total cost path

to volume using HardCopy^®IV ASICs for all the family variants, a comprehensive

portfolio of application solutions customized for end-markets, and the industry

leading Quartus^®II software to increase productivity and performance.

For information about upcoming Stratix IV device features, refer to the Upcoming

Stratix IV Device Features document.

For information about changes to the currently published Stratix IV Device Handbook,

refer to the Addendum to the Stratix IV Device Handbook chapter.

This chapter contains the following sections:

■

“Feature Summary” on page 1–2

“Architecture Features” on page 1–6

“Integrated Software Platform” on page 1–19

“Ordering Information” on page 1–19

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

Stratix IV Device Handbook

Volume 1

January 2016

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与EP4SE230F29C2N相关器件

型号	品牌	获取价格	描述	数据表
EP4SE230F29C3	INTEL	获取价格	Field Programmable Gate Array, 9120 CLBs, 717MHz, 228000-Cell, CMOS, PBGA780, 29 X 29 MM,
EP4SE230F29C3	ALTERA	获取价格	Field Programmable Gate Array, 9120 CLBs, 717MHz, 228000-Cell, CMOS, PBGA780, 29 X 29 MM,
EP4SE230F29C3N	ALTERA	获取价格	Field Programmable Gate Array, 9120 CLBs, 717MHz, 228000-Cell, CMOS, PBGA780, 29 X 29 MM,
EP4SE230F29C3N	INTEL	获取价格	Field Programmable Gate Array, 9120 CLBs, 717MHz, 228000-Cell, CMOS, PBGA780, 29 X 29 MM,
EP4SE230F29C4	ALTERA	获取价格	Field Programmable Gate Array, 9120 CLBs, 717MHz, 228000-Cell, CMOS, PBGA780, 29 X 29 MM,
EP4SE230F29C4	INTEL	获取价格	Field Programmable Gate Array, 9120 CLBs, 717MHz, 228000-Cell, CMOS, PBGA780, 29 X 29 MM,
EP4SE230F29C4N	INTEL	获取价格	Field Programmable Gate Array, 9120 CLBs, 717MHz, 228000-Cell, CMOS, PBGA780, 29 X 29 MM,
EP4SE230F29C4N	ALTERA	获取价格	Field Programmable Gate Array, 9120 CLBs, 717MHz, 228000-Cell, CMOS, PBGA780, 29 X 29 MM,
EP4SE230F29I2	INTEL	获取价格	Field Programmable Gate Array,
EP4SE230F29I2N	INTEL	获取价格	Field Programmable Gate Array,

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