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EP4SE230F29I4N

更新时间： 2024-12-01 19:22:07
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟栅可编程逻辑
页数 文件大小 规格书
22页 497K
描述
Field Programmable Gate Array, 9120 CLBs, 717MHz, 228000-Cell, CMOS, PBGA780, 29 X 29 MM, LEAD FREE, FBGA-780

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EP4SE230F29I4N 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：BGA
包装说明：29 X 29 MM, LEAD FREE, FBGA-780针数：780
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：3.59最大时钟频率：717 MHz
JESD-30 代码：S-PBGA-B780JESD-609代码：e1
长度：29 mm湿度敏感等级：4
可配置逻辑块数量：9120输入次数：488
逻辑单元数量：228000输出次数：488
端子数量：780组织：9120 CLBS
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA780,28X28,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：245
电源：0.9,1.2/3,1.5,2.5 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：3.4 mm
子类别：Field Programmable Gate Arrays最大供电电压：0.93 V
最小供电电压：0.87 V标称供电电压：0.9 V
表面贴装：YES技术：CMOS
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：40宽度：29 mm
Base Number Matches：1

EP4SE230F29I4N 数据手册

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1. Overview for the Stratix IV Device  
Family  
January 2016  
SIV51001-3.5  
SIV51001-3.5  
Altera® Stratix® IV FPGAs deliver a breakthrough level of system bandwidth and  
power efficiency for high-end applications, allowing you to innovate without  
compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor  
Manufacturing Company (TSMC) 40-nm process technology and surpass all other  
high-end FPGAs, with the highest logic density, most transceivers, and lowest power  
requirements.  
The Stratix IV device family contains three optimized variants to meet different  
application requirements:  
■
Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 kilobits  
(Kb) RAM, and 1,288 18 x 18 bit multipliers  
■
Stratix IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kb RAM, 1,288  
18 x 18-bit multipliers, and 48 full-duplex clock data recovery (CDR)-based  
transceivers at up to 8.5 Gbps  
■
Stratix IV GT—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers,  
and 48 full-duplex CDR-based transceivers at up to 11.3 Gbps  
The complete Altera high-end solution includes the lowest risk, lowest total cost path  
to volume using HardCopy® IV ASICs for all the family variants, a comprehensive  
portfolio of application solutions customized for end-markets, and the industry  
leading Quartus® II software to increase productivity and performance.  
f
f
For information about upcoming Stratix IV device features, refer to the Upcoming  
Stratix IV Device Features document.  
For information about changes to the currently published Stratix IV Device Handbook,  
refer to the Addendum to the Stratix IV Device Handbook chapter.  
This chapter contains the following sections:  
■
■
■
■
“Feature Summary” on page 1–2  
“Architecture Features” on page 1–6  
“Integrated Software Platform” on page 1–19  
“Ordering Information” on page 1–19  
© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos  
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as  
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its  
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and  
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service  
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying  
on any published information and before placing orders for products or services.  
ISO  
9001:2008  
Registered  
Stratix IV Device Handbook  
Volume 1  
January 2016  
Feedback Subscribe  
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