Datasheet > EP20K400BC672-1

EP20K400BC672-1

更新时间： 2024-11-09 06:50:39

品牌	Logo	应用领域
阿尔特拉 - ALTERA		/
页数	文件大小	规格书
68页	930K
描述
Loadable PLD, PBGA672

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EP20K400BC672-1 数据手册

APEX 20K

Programmable Logic

Device Family

August 1999, ver. 2.01

Data Sheet

■

Industry’s first programmable logic device (PLD) incorporating

System-on-a-Programmable-Chip^TMintegration

–

Features...

MultiCore^TMarchitecture integrating look-up table (LUT) logic,

product-term logic, and embedded memory

–

Embedded system block (ESB) implementation of product-term

logic used for combinatorial-intensive functions

LUT logic used for register-intensive functions

ESB used to implement memory functions, including first-in

first-out (FIFO) buffers, dual-port RAM, and content-

addressable memory (CAM)

–

Preliminary

Information

■

High density

–

100,000 to 1 million typical gates (see Table 1)

Up to 38,400 logic elements (LEs)

Up to 327,680 RAM bits that can be used without reducing

available logic

–

Up to 2,560 product-term-based macrocells

Table 1. APEX 20K Device Features

Notes (1), (2)

EP20K60E EP20K100E EP20K160E EP20K200E EP20K300E EP20K400E

EP20K600E EP20K1000E EP20K1500E

Feature

EP20K100

EP20K200

EP20K400

Maximum 162,000 263,000 404,000 526,000 728,000 1,052,000 1,537,000 1,771,520 2,524,416

system

gates

Typical

gates

60,000 100,000 160,000 200,000 300,000 400,000

600,000 1,000,000 1,500,000

LEs

2,560

4,160

6,400

8,320

11,520

16,640

104

24,320

152

38,400

160

54,720

228

ESBs

Maximum

RAM bits

32,768 53,248

81,920 106,496 147,456 212,992

311,296

327,680

466,944

Maximum

256

204

416

252

640

316

832

382

1,152

408

1,664

502

2,432

624

2,560

716

3,648

858

macrocells

Maximum

user I/O

pins

Notes:

(1) The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to 48,000

additional gates.

(2) This information is preliminary.

Altera Corporation

A-DS-APEX20K-02.01

12 3 4 5 6 7...68

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