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EP20K100TC144-2ES PDF预览

EP20K100TC144-2ES

更新时间: 2024-11-06 23:50:43
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
116页 1425K
描述
FPGA

EP20K100TC144-2ES 数据手册

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APEX 20K  
Programmable Logic  
Device Family  
®
December 2001, ver. 4.2  
Data Sheet  
Industry’s first programmable logic device (PLD) incorporating  
system-on-a-programmable-chip (SOPC) integration  
Features...  
MultiCoreTM architecture integrating look-up table (LUT) logic,  
product-term logic, and embedded memory  
LUT logic used for register-intensive functions  
Embedded system block (ESB) used to implement memory  
functions, including first-in first-out (FIFO) buffers, dual-port  
RAM, and content-addressable memory (CAM)  
ESB implementation of product-term logic used for  
combinatorial-intensive functions  
High density  
30,000 to 1.5 million typical gates (see Tables 1 and 2)  
Up to 51,840 logic elements (LEs)  
Up to 442,368 RAM bits that can be used without reducing  
available logic  
Up to 3,456 product-term-based macrocells  
Table 1. APEX 20K Device Features  
Note (1)  
Feature  
EP20K30E EP20K60E EP20K100 EP20K100E EP20K160E EP20K200  
EP20K200E  
Maximum  
system  
gates  
113,000  
162,000  
263,000  
263,000  
404,000  
526,000  
526,000  
Typical  
gates  
30,000  
60,000  
100,000  
100,000  
160,000  
200,000  
200,000  
LEs  
1,200  
12  
2,560  
16  
4,160  
26  
4,160  
26  
6,400  
40  
8,320  
52  
8,320  
52  
ESBs  
Maximum  
RAM bits  
24,576  
32,768  
53,248  
53,248  
81,920  
106,496  
106,496  
Maximum  
macrocells  
192  
128  
256  
196  
416  
252  
416  
246  
640  
316  
832  
382  
832  
376  
Maximum  
user I/O  
pins  
Altera Corporation  
1
A-DS-APEX20K-04.2  

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