Datasheet > EP20K1000CF672C-8

EP20K1000CF672C-8

更新时间： 2024-02-12 09:13:36

品牌	Logo	应用领域
英特尔 - INTEL		LTE 输入元件可编程逻辑
页数	文件大小	规格书
94页	780K
描述
LOADABLE PLD, 1.79ns, PBGA672, 27 X 27 MM, 1 MM PITCH, FBGA-672

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EP20K1000CF672C-8 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	27 X 27 MM, 1 MM PITCH, FBGA-672	针数：	672
Reach Compliance Code：	compliant	风险等级：	5.12
JESD-30 代码：	S-PBGA-B672	JESD-609代码：	e0
长度：	27 mm	专用输入次数：	4
I/O 线路数量：	508	端子数量：	672
最高工作温度：	85 °C	最低工作温度：
组织：	4 DEDICATED INPUTS, 508 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	220	可编程逻辑类型：	LOADABLE PLD
传播延迟：	1.79 ns	认证状态：	Not Qualified
座面最大高度：	3.5 mm	最大供电电压：	1.89 V
最小供电电压：	1.71 V	标称供电电压：	1.8 V
表面贴装：	YES	温度等级：	OTHER
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	27 mm
Base Number Matches：	1

EP20K1000CF672C-8 数据手册

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APEX 20KC Programmable Logic Device Data Sheet

After an APEX 20KC device has been configured, it can be reconfigured

in-circuit by resetting the device and loading new data. Real-time changes

can be made during system operation, enabling innovative reconfigurable

computing applications.

APEX 20KC devices are supported by the Altera Quartus II development

system, a single, integrated package that offers HDL and schematic design

entry, compilation and logic synthesis, full simulation and worst-case

timing analysis, SignalTap logic analysis, and device configuration. The

Quartus II software runs on Windows-based PCs, Sun SPARCstations,

and HP 9000 Series 700/800 workstations.

The Quartus II software provides NativeLink interfaces to other industry-

standard PC- and UNIX workstation-based EDA tools. For example,

designers can invoke the Quartus II software from within third-party

design tools. Further, the Quartus II software contains built-in optimized

synthesis libraries; synthesis tools can use these libraries to optimize

designs for APEX 20KC devices. For example, the Synopsys Design

Compiler library, supplied with the Quartus II development system,

includes DesignWare functions optimized for the APEX 20KC

architecture.

APEX 20KC devices incorporate LUT-based logic, product-term-based

logic, and memory into one device on an all-copper technology process.

Signal interconnections within APEX 20KC devices (as well as to and from

device pins) are provided by the FastTrack interconnect—a series of fast,

continuous row and column channels that run the entire length and width

of the device.

Functional

Description

Each I/O pin is fed by an I/O element (IOE) located at the end of each row

and column of the FastTrack interconnect. Each IOE contains a

bidirectional I/O buffer and a register that can be used as either an input

or output register to feed input, output, or bidirectional signals. When

used with a dedicated clock pin, these registers provide exceptional

performance. IOEs provide a variety of features, such as 3.3-V, 64-bit,

66-MHz PCI compliance; JTAG BST support; slew-rate control; and

tri-state buffers. APEX 20KC devices offer enhanced I/O support,

including support for 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, LVPECL,

3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, and 3.3-V

AGP I/O standards.

Altera Corporation

1...4 5 678 9 10...94

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与EP20K1000CF672C-8相关器件

型号	品牌	描述	获取价格	数据表
EP20K1000CF672C9N	INTEL	Loadable PLD, 2.02ns, PBGA672, 27 X 27 MM, 1 MM PITCH, FBGA-672	获取价格
EP20K1000CF672I7ES	ETC	ASIC	获取价格
EP20K1000CF672I8ES	ETC	ASIC	获取价格
EP20K1000CF672I9ES	ETC	ASIC	获取价格
EP20K1000E	ALTERA	Programmable Logic Device Family	获取价格
EP20K1000EBC652-1ES	ETC	FPGA	获取价格

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