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EP20K1000EFC33-1X PDF预览

EP20K1000EFC33-1X

更新时间: 2024-02-28 17:30:17
品牌 Logo 应用领域
阿尔特拉 - ALTERA 输入元件可编程逻辑
页数 文件大小 规格书
117页 593K
描述
Loadable PLD, 1.84ns, CMOS, PBGA1020, FINE LINE, BGA-1020

EP20K1000EFC33-1X 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:BGA
包装说明:FINE LINE, BGA-1020针数:1020
Reach Compliance Code:not_compliantECCN代码:3A001.A.7.A
HTS代码:8542.39.00.01风险等级:5.11
JESD-30 代码:S-PBGA-B1020JESD-609代码:e0
长度:33 mm湿度敏感等级:3
专用输入次数:4I/O 线路数量:708
输入次数:700逻辑单元数量:38400
输出次数:700端子数量:1020
最高工作温度:85 °C最低工作温度:
组织:4 DEDICATED INPUTS, 708 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA1020,32X32,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):220
电源:1.8,1.8/3.3 V可编程逻辑类型:LOADABLE PLD
传播延迟:1.84 ns认证状态:Not Qualified
座面最大高度:3.5 mm子类别:Field Programmable Gate Arrays
最大供电电压:1.89 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:33 mm
Base Number Matches:1

EP20K1000EFC33-1X 数据手册

 浏览型号EP20K1000EFC33-1X的Datasheet PDF文件第2页浏览型号EP20K1000EFC33-1X的Datasheet PDF文件第3页浏览型号EP20K1000EFC33-1X的Datasheet PDF文件第4页浏览型号EP20K1000EFC33-1X的Datasheet PDF文件第5页浏览型号EP20K1000EFC33-1X的Datasheet PDF文件第6页浏览型号EP20K1000EFC33-1X的Datasheet PDF文件第7页 
APEX 20K  
Programmable Logic  
Device Family  
March 2004, ver. 5.1  
Data Sheet  
Industry’s first programmable logic device (PLD) incorporating  
system-on-a-programmable-chip (SOPC) integration  
Features  
MultiCoreTM architecture integrating look-up table (LUT) logic,  
product-term logic, and embedded memory  
LUT logic used for register-intensive functions  
Embedded system block (ESB) used to implement memory  
functions, including first-in first-out (FIFO) buffers, dual-port  
RAM, and content-addressable memory (CAM)  
ESB implementation of product-term logic used for  
combinatorial-intensive functions  
High density  
30,000 to 1.5 million typical gates (see Tables 1 and 2)  
Up to 51,840 logic elements (LEs)  
Up to 442,368 RAM bits that can be used without reducing  
available logic  
Up to 3,456 product-term-based macrocells  
Table 1. APEX 20K Device Features Note (1)  
Feature  
EP20K30E EP20K60E EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E  
Maximum  
system  
gates  
113,000  
162,000  
263,000  
263,000  
404,000  
526,000  
526,000  
Typical  
gates  
30,000  
60,000  
100,000  
100,000  
160,000  
200,000  
200,000  
LEs  
1,200  
12  
2,560  
16  
4,160  
26  
4,160  
26  
6,400  
40  
8,320  
52  
8,320  
52  
ESBs  
Maximum  
RAM bits  
24,576  
32,768  
53,248  
53,248  
81,920  
106,496  
106,496  
Maximum  
macrocells  
192  
128  
256  
196  
416  
252  
416  
246  
640  
316  
832  
382  
832  
376  
Maximum  
user I/O  
pins  
Altera Corporation  
1
DS-APEX20K-5.1  
 

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