Datasheet > EP20K1000CF1020I7ES

EP20K1000CF1020I7ES

更新时间： 2022-01-18 20:48:00

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
86页	1020K
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ASIC

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APEX 20KC Programmable Logic Device Data Sheet

After an APEX 20KC device has been configured, it can be reconfigured

in-circuit by resetting the device and loading new data. Real-time changes

can be made during system operation, enabling innovative reconfigurable

computing applications.

APEX 20KC devices are supported by the Altera Quartus II development

system, a single, integrated package that offers HDL and schematic design

entry, compilation and logic synthesis, full simulation and worst-case

timing analysis, SignalTap logic analysis, and device configuration. The

Quartus II software runs on Windows-based PCs, Sun SPARCstations,

and HP 9000 Series 700/800 workstations.

The Quartus II software provides NativeLink interfaces to other industry-

standard PC- and UNIX workstation-based EDA tools. For example,

designers can invoke the Quartus II software from within third-party

design tools. Further, the Quartus II software contains built-in optimized

synthesis libraries; synthesis tools can use these libraries to optimize

designs for APEX 20KC devices. For example, the Synopsys Design

Compiler library, supplied with the Quartus II development system,

includes DesignWare functions optimized for the APEX 20KC

architecture.

APEX 20KC devices incorporate LUT-based logic, product-term-based

logic, and memory into one device on an all-copper technology process.

Signal interconnections within APEX 20KC devices (as well as to and from

device pins) are provided by the FastTrack interconnect—a series of fast,

continuous row and column channels that run the entire length and width

of the device.

Functional

Description

Each I/O pin is fed by an I/O element (IOE) located at the end of each row

and column of the FastTrack interconnect. Each IOE contains a

bidirectional I/O buffer and a register that can be used as either an input

or output register to feed input, output, or bidirectional signals. When

used with a dedicated clock pin, these registers provide exceptional

performance. IOEs provide a variety of features, such as 3.3-V, 64-bit,

66-MHz PCI compliance; JTAG BST support; slew-rate control; and

tri-state buffers. APEX 20KC devices offer enhanced I/O support,

including support for 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, LVPECL,

3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, and 3.3-V

AGP I/O standards.

Altera Corporation

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与EP20K1000CF1020I7ES相关器件

型号	品牌	获取价格	描述	数据表
EP20K1000CF1020I8ES	ETC	获取价格	ASIC
EP20K1000CF1020I9ES	ETC	获取价格	ASIC
EP20K1000CF33C7	ALTERA	获取价格	Loadable PLD, 1.49ns, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020
EP20K1000CF33C8	ETC	获取价格	FPGA
EP20K1000CF33C9	ALTERA	获取价格	Loadable PLD, 2.02ns, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020
EP20K1000CF33C9N	INTEL	获取价格	Loadable PLD, 2.02ns, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020
EP20K1000CF33I8	ETC	获取价格	FPGA
EP20K1000CF672C7	INTEL	获取价格	Loadable PLD, 1.49ns, CMOS, PBGA672, 27 X 27 MM, 1 MM PITCH, FBGA-672
EP20K1000CF672C-7	INTEL	获取价格	LOADABLE PLD, 1.49ns, PBGA672, 27 X 27 MM, 1 MM PITCH, FBGA-672
EP20K1000CF672C8	ALTERA	获取价格	Programmable Logic Device

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